CPRI IP User Guide

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ID 683595
Date 6/13/2025
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Document Table of Contents
Document Table of Contents x
1. About the CPRI IP 2. Getting Started with the CPRI IP 3. CPRI IP Functional Description 4. CPRI IP Signals 5. CPRI IP Registers 6. CPRI Altera® FPGA IP User Guide Archives 7. Document Revision History for the CPRI IP User Guide
1. About the CPRI IP x
1.1. CPRI IP Features 1.2. CPRI IP Device Family and Speed Grade Support 1.3. IP Verification 1.4. Resource Utilization for CPRI IP 1.5. CPRI IP Release Information
1.2. CPRI IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI IP x
2.1. Installation and Licensing 2.2. Generating a CPRI IP 2.3. CPRI IP Parameters 2.4. Integrating the CPRI IP into your Design: Required External Blocks 2.5. Simulating Intel FPGA IP Cores 2.6. Running the CPRI IP Design Example 2.7. CPRI IP Design Example Clocks 2.8. About the Testbench 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Generating a CPRI IP x
2.2.1. CPRI IP Generated Files
2.4. Integrating the CPRI IP into your Design: Required External Blocks x
2.4.1. Adding the Transceiver TX PLL IP 2.4.2. Adding the Reset Controller 2.4.3. Adding the Transceiver Reconfiguration Controller 2.4.4. Adding the Off-Chip Clean-Up PLL 2.4.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.4.6. CPRI IP Transceiver PLL Calibration 2.4.7. Reference and System PLL Clock for your IP Design
2.4.7. Reference and System PLL Clock for your IP Design x
2.4.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.4.7.2. System PLL Connections for the Agilex 5 Variations 2.4.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI IP Clocking Structure 3.3. CPRI IP Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. CPRI IP Deterministic Latency 3.19. CPRI IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI IP Clocking Structure x
3.2.1. Example CPRI IP Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.19. CPRI IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI IP Loopback Modes 3.20.2. CPRI IP Self-Synchronization Feature
4. CPRI IP Signals x
4.1. CPRI IP Core L2 Interface 4.2. CPRI IP Core L1 Direct Access Interfaces 4.3. CPRI IP Core Management Interfaces 4.4. CPRI IP Core Transceiver and Transceiver Management Signals
1. About the CPRI IP
2. Getting Started with the CPRI IP
3. CPRI IP Functional Description
4. CPRI IP Signals
5. CPRI IP Registers
6. CPRI Altera® FPGA IP User Guide Archives
7. Document Revision History for the CPRI IP User Guide

2.4.5. Adding and Connecting the Single-Trip Delay Calibration Blocks

If you turn on Enable single-trip delay calibration in the CPRI parameter editor, and for Synchronization mode select Agent, the CPRI IP requires that you connect the IOPLL (pll_core block) and the Dynamic Phase Control Unit (DPCU) (pll_dpcu block). You must generate a device core PLL to create the IOPLL. Altera® provides the DPCU block with the CPRI IP, but you must connect it, and the IOPLL, in your design. A single IOPLL block and a single DPCU block can connect to multiple CPRI IPs.
Figure 7. Connecting a Single DPCU Block and Single IOPLL Block to Multiple CPRI IP Cores
  1. Generate a non-transceiver PLL IP to create the IOPLL block. You can use the IP Catalog to generate the external PLL IP that configures a core PLL on the device.
  2. In the IP Catalog, select an IP that configures an appropriate PLL on your target device.
  3. For your Arria® 10 design, you must select Arria 10 FPLL in the IP Catalog.
  4. In the parameter editor for the fPLL IP, you must set the following parameter values:
    • Set fPLL Mode to Core.
    • Set the PLL output frequency to the expected input frequency for the CPRI IP cpri_coreclk input signal.
    • Turn on Enable access to dynamic phase shift ports.
  5. Connect the IOPLL and DPCU signals to the CPRI IP signals according to the following rules. Refer to Example CPRI IP Clock Connections in Different Clocking Modes for an illustration of the clock connections.
    Table 15.  Required Connections to and From IOPLL Block in CPRI Design With Single-Trip Delay Calibration
    IOPLL Block Signal Connect to
    cntsel (input) DPCU pll_cntsel output signal
    num_phase_shifts (input) DPCU pll_num_phase_shifts output signal
    outclk_0 (output) CPRI IP cpri_coreclk input clock signal
    phase_done (output) DPCU pll_phase_done input signal
    phase_en (input) DPCU pll_phase_en output signal
    refclk (input) CPRI IP tx_clkout output signal or output from the off-chip clean-up PLL
    rst (input) Drive with the inverse of the CPRI IP reset_n input signal
    scanclk (input) DPCU pll_scanclk output signal
    updn (input) DPCU pll_updn output signal
    Table 16.  Required Connections to and From DPCU Block in CPRI Design With Single-Trip Delay Calibration
    DPCU Block Signal Connect to
    clk Drive in the frequency range of 100–150 MHz.
    Note: Altera® recommends that you drive this DPCU input clock with the source for the reconfig_clk.
    reset_n (input) CPRI IP reset_n input signal
    csr_bit_rate (input) If you turned on Enable line bit rate auto-negotiation in the CPRI parameter editor, connect to the CPRI IP nego_bitrate_out[5:0] output signal.

    If autorate negotiation is not turned on, hardwire the DPCU csr_bit_rate signal to the encoded value for the CPRI line bit rate:

    • 6'b000001: 0.6144 Gbps
    • 6'b000010: 1.2288 Gbps
    • 6'b000100: 2.4576 Gbps
    • 6'b000101: 3.0720 Gbps
    • 6'b001000: 4.9150 Gbps
    • 6'b001010: 6.1440 Gbps
    • 6'b010110: 8.11008 Gbps
    • 6'b010000: 9.8304 Gbps
    • 6'b010100: 10.1376 Gbps
    • 6b'011000: 12.16512 Gbps
    • 6'b110000 : 24.33024 Gbps
    cal_status (output) CPRI IP cal_status input signal
    cal_ctrl (input) CPRI IP cal_ctrl output signal
    pll_cntsel (output) IOPLL cntsel input signal
    pll_num_phase_shifts (output) IOPLL num_phase_shifts input signal
    pll_phase_done (input) IOPLL phase_done output signal
    pll_phase_en (output) IOPLL phase_en input signal
    pll_scanclk (output) IOPLL scanclk input signal
    pll_updn (output) IOPLL updn input signal

    Your logic must provide the connections. Refer to the Figure: CPRI Agent IP in External Clocking Mode with Single-Trip Delay Calibration Feature for Arria® 10 Device Variations

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