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3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Intel Agilex® 7 HPS Component Revision History
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2.3.1.3. Peripheral FPGA Clocks
Figure 15. Platform Designer Peripheral FPGA Clocks Sub-Window
The table below provides a description for each of the parameters in the "Peripheral FPGA Clocks" sub-window.
Parameter Name | Parameter Description |
---|---|
EMAC 0 (emac0_md_clk clock frequency) | If EMAC 0 peripheral is routed to FPGA, use the input field to specify EMAC 0 MDIO clock frequency |
EMAC 0 (emac0_gtx_clk clock frequency) | If EMAC 0 peripheral is routed to FPGA, use the input field to specify EMAC 0 transmit clock frequency |
EMAC 1 (emac1_md_clk clock frequency) | If EMAC 1 peripheral is routed to FPGA, use the input field to specify EMAC 1 MDIO clock frequency |
EMAC 1 (emac1_gtx_clk clock frequency) | If EMAC 1 peripheral is routed to FPGA, use the input field to specify EMAC 1 transmit clock frequency |
EMAC 2 (emac2_md_clk clock frequency) | If EMAC 2 peripheral is routed to FPGA, use the input field to specify EMAC 2 MDIO clock frequency |
EMAC 2 (emac2_gtx_clk clock frequency) | If EMAC 2 peripheral is routed to FPGA, use the input field to specify EMAC 2 transmit clock frequency |
SD/MMC (sdmmc_cclk) | If this peripheral pin multiplexing is configured to route to FPGA fabric, use the input field to specify the SD/MMC sdmmc_cclk clock frequency |
SPIM 0 (spim0_sclk_out clock frequency) | If SPI master 0 peripheral is routed to FPGA, use the input field to specify SPI master 0 output clock frequency |
SPIM 1 (spim1_sclk_out clock frequency) | If SPI master 1 peripheral is routed to FPGA, use the input field to specify SPI master 1 output clock frequency |
I2C0 (i2c0_clk clock frequency) | If I2C 0 peripheral is routed to FPGA, use the input field to specify I2C 0 output clock frequency |
I2C1 (i2c1_clk clock frequency) | If I2C 1 peripheral is routed to FPGA, use the input field to specify I2C 1 output clock frequency |
I2CEMAC0 (i2cemac0_clk) | If this peripheral pin multiplexing is configured to route to the FPGA fabric, use the input field to specify the I2CEMAC0 i2cemac0_clk clock frequency |
I2CEMAC1 (i2cemac1_clk) | If this peripheral pin multiplexing is configured to route to the FPGA fabric, use the input field to specify the I2CEMAC1 i2cemac1_clk clock frequency |
I2CEMAC2 (i2cemac2_clk) | If this peripheral pin multiplexing is configured to route to the FPGA fabric, use the input field to specify the I2CEMAC2 i2cemac2_clk clock frequency |