Intel Agilex® 7 Hard Processor System Component Reference Manual

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ID 683581
Date 4/10/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel Agilex® 7 Hard Processor System Component 2. Configuring the Intel Agilex® 7 Hard Processor System Component 3. Simulating the Intel Agilex® 7 HPS Component
1. Introduction to the Intel Agilex® 7 Hard Processor System Component x
1.1. Cortex*-A53 MPCore* Processor 1.2. CoreSight* Debug Components 1.3. Interconnect 1.4. FPGA Bridges 1.5. Memory Controllers 1.6. Support Peripherals 1.7. Introduction to the HPS Component Revision History
1.6. Support Peripherals x
1.6.1. Interface Peripherals 1.6.2. On-Chip Memories
2. Configuring the Intel Agilex® 7 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. FPGA Interfaces 2.3. HPS Clocks and Resets 2.4. HPS EMIF 2.5. I/O Delays 2.6. Pin MUX and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the HPS Component Revision History
2.2. FPGA Interfaces x
2.2.1. General Interfaces 2.2.2. HPS-FPGA AXI Bridges 2.2.3. HPS Boot Source 2.2.4. DMA Controller Interface 2.2.5. Interrupts
2.2.1. General Interfaces x
2.2.1.1. Enable MPU Standby and Event Interfaces 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable FPGA Cross Trigger Interface 2.2.1.6. Enable DDR Arm* Trace Bus (ATB)
2.2.2. HPS-FPGA AXI Bridges x
2.2.2.1. FPGA-to-HPS Slave Interface 2.2.2.2. HPS to FPGA AXI-4 Master Interface 2.2.2.3. Lightweight HPS to FPGA Master Interface
2.2.5. Interrupts x
2.2.5.1. FPGA-to-HPS 2.2.5.2. HPS-to-FPGA
2.3. HPS Clocks and Resets x
2.3.1. Input Clocks 2.3.2. Internal Clocks and Output Clocks 2.3.3. Resets
2.3.1. Input Clocks x
2.3.1.1. External Clock Source 2.3.1.2. FPGA-to-HPS Clocks Source 2.3.1.3. Peripheral FPGA Clocks
2.3.2. Internal Clocks and Output Clocks x
2.3.2.1. Main PLL Output Clocks – Desired Frequencies 2.3.2.2. HPS to FPGA User Clocks 2.3.2.3. HPS Peripheral Clocks – Desired Frequencies 2.3.2.4. Clock Sources 2.3.2.5. PLL Report
2.6. Pin MUX and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. Pin Mux Report 2.6.3. EMAC ptp Interface
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
3. Simulating the Intel Agilex® 7 HPS Component x
3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the Intel Agilex® 7 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. Running the Simulations
3.1.1. Setting Up the HPS Component for Simulation x
3.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
3.1.3. Running the Simulations x
3.1.3.1. Running HPS RTL Simulation 3.1.3.2. Running HPS Post-Fit Simulation
3.1.3.2. Running HPS Post-Fit Simulation x
3.1.3.2.1. Post-Fit Simulation Files 3.1.3.2.2. BFM API Hierarchy Format
3.2. Clock and Reset Interfaces x
3.2.1. Clock Interface 3.2.2. Reset Interface
1. Introduction to the Intel Agilex® 7 Hard Processor System Component
2. Configuring the Intel Agilex® 7 Hard Processor System Component
3. Simulating the Intel Agilex® 7 HPS Component

2.2.5.2. HPS-to-FPGA

Table 4.  HPS-to-FPGA Interrupts InterfaceThe following table lists the available HPS to FPGA interrupt interfaces and the corresponding interfaces available when they are enabled.
Parameter Name Parameter Description Interface Name
Enable Clock Peripheral Interrupts Enables interface for HPS clock manager and MPU wake-up interrupt signals to the FPGA h2f_clkmgr_interrupt
Enable DMA Interrupts Enables interface for HPS DMA channels interrupt and DMA abort interrupt to the FPGA

h2f_dma_interrupt0

h2f_dma_interrupt1

h2f_dma_interrupt2

h2f_dma_interrupt3

h2f_dma_interrupt4

h2f_dma_interrupt5

h2f_dma_interrupt6

h2f_dma_interrupt7

h2f_dma_abort_interrupt

Enable EMAC Interrupts Enables interface for HPS Ethernet MAC controller interrupt to the FPGA. EMAC must be enabled in Pin Mux Tab before enabling interrupt.

h2f_emac0_interrupt

h2f_emac1_interrupt

h2f_emac2_interrupt

Enable GPIO Interrupts Enables interface for the HPS general purpose IO (GPIO) interrupt to the FPGA

h2f_gpio0_interrupt

h2f_gpio1_interrupt

h2f_gpio2_interrupt

Enable I2C-EMAC Interrupts Enable the HPS peripheral interrupt for I2CEMAC to be driven into the FPGA fabric

h2f_i2c_emac0_interrupt

h2f_i2c_emac1_interrupt

h2f_i2c_emac2_interrupt

Enable I2C Peripherals Interrupts Enable the HPS peripheral interrupt for I2C0 to be driven into the FPGA fabric. The I2C must be enabled in the Pin Mux Tab before enabling interrupt.

h2f_i2c0_interrupt

h2f_i2c1_interrupt

Enable L4 Timer Interrupts Enables the HPS peripheral interrupt for L4TIMER to be driven into the FPGA fabric.

h2f_timer_l4sp_0_interrupt

h2f_timer_l4sp_1_interrupt

Enable NAND Interrupts Enables interface for the HPS NAND controller interrupt to the FPGA. The NAND IP Block must be enabled in Pin Mux Tab before enabling interrupt.

h2f_nand_interrupt

Enable SYS Timer Interrupts Enables the HPS peripheral interrupt for SYSTIMER to be driven into the FPGA fabric.

h2f_timer_sys_0_interrupt

h2f_timer_sys_1_interrupt

Enable SD/MMC Interrupts Enables interface for the HPS SD/MMC controller interrupt to the FPGA. The SD/MMC IP Block must be enabled in Pin Mux Tab before enabling interrupt.

h2f_sdmmc_interrupt

Enable SPI Master Interrupts Enables interface for the HPS SPI master controller interrupt to the FPGA. The SPI Master IP Block must be enabled in Pin Mux Tab before enabling interrupt.

h2f_spim0_interrupt

h2f_spim1_interrupt

Enable SPI Slave Interrupts Enables interface for the HPS SPI slave controller interrupt to the FPGA. The SPI IP Block must be enabled in Pin Mux Tab before enabling interrupt.

h2f_spis0_interrupt

h2f_spis1_interrupt

Enable ECC/Parity_L1 Interrupts Enables the HPS peripheral interrupt for ECC single and double bit error and L1 parity error to be driven into the FPGA fabric.

h2f_ecc_serr_interrupt

h2f_ecc_derr_interrupt

h2f_parity_l1_interrupt

Enable UART Interrupts Enables interface for the HPS UART controller interrupt to the FPGA. The UART IP Block must be enabled in Pin Mux Tab before enabling interrupt.

h2f_uart0_interrupt

h2f_uart1_interrupt

Enable USB Interrupts Enables interface for the HPS USB controller interrupt to the FPGA. The USB IP Block must be enabled in Pin Mux Tab before enabling interrupt.

h2f_usb0_interrupt

h2f_usb1_interrupt

Enable Watchdog Interrupts Enables interface for the HPS watchdog interrupt to the FPGA

h2f_wdog0_interrupt

h2f_wdog1_interrupt

Level Two Title