AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

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ID 683560
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices A. Reference Design Files
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping 1.1.3. Floorplanning
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Installing the Intel® Stratix® 10 GX FPGA Development Kit 1.2.3. Installing the Linux Driver 1.2.4. Bringing Up the Reference Design
1.3. Reference Design Components x
1.3.1. BSP Top
1.3.1. BSP Top x
1.3.1.1. PCI Express* IP core 1.3.1.2. Intel® Stratix® 10 DDR4 External Memory Interfaces IP Core 1.3.1.3. Design Top
1.3.1.3. Design Top x
1.3.1.3.1. Global Reset Logic 1.3.1.3.2. PR Region Wrapper 1.3.1.3.3. Intel® Stratix® 10 Partial Reconfiguration Region Controller IP Core 1.3.1.3.4. Intel® Stratix® 10 Partial Reconfiguration Controller IP Core 1.3.1.3.5. Partial Reconfiguration Logic
1.5. Testing the Reference Design x
1.5.1. program_fpga_jtag 1.5.2. fpga-configure example_host_uio
example_host_uio x
1.5.3.1. Compiling the Example Applications 1.5.3.2. Programming the Design Using Example Applications
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
A. Reference Design Files

1.5.2. fpga-configure

Use the fpga-configure utility to perform partial reconfiguration. The script accepts a .rbf file for a given persona. The script performs the following functions:
  • Communicates with the driver to remove device sub-drivers, if any
  • Communicates with the fpga-region-controller script to assert/de-assert freeze
  • Writes the .rbf to the Partial Reconfiguration Controller IP core
  • Re-deploys the sub-drivers, if any, that are required upon successful PR
To perform PR over PCIe* , run the following command: 
fpga-configure -p <path-to-rbf> <region_controller_addr>
Table 8.   fpga-configure Command-Line Options
Option Description
-p

Performs partial reconfiguration over PCIe* programming.

-d

Disables the advanced error reporting on the PCIe* link. Advanced error reporting generally reports any critical errors along the PCIe* link, directly to the kernel. If the PCIe* link is completely disabled, the kernel responds by crashing the system. You must disable advanced error reporting during full chip configuration, as full chip configuration brings down the PCIe* link.

-e

Enables the advanced error reporting for the PCIe* link. Use this option after full chip configuration to ensure the integrity of the PCIe* link.

-r

Prints the contents of a debug ROM within the reference design. Use for debug purposes.

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