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Ixiasoft
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Ixiasoft
10. Cache and Tightly-Coupled Memory
Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios® II processor. Fortunately, most software based on the Nios® II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly.
For code that needs direct control over the cache, the Nios® II architecture provides facilities to perform the following actions:
- Initialize lines in the instruction and data caches
- Flush lines in the instruction and data caches
- Bypass the data cache during load and store instructions
This chapter discusses the following common cases in which you must manage the cache:
- Initializing cache after reset
- Writing device drivers
- Writing program loaders
- Managing cache in multi-master or multi-processor systems
This chapter covers cache management issues that affect Nios® II programmers. It does not discuss the fundamental operation of caches. Refer to The Cache Memory Book by Jim Handy for a discussion of general cache management issues.
Section Content
Nios II Cache Implementation
HAL API Functions for Managing Cache
Initializing the Nios II Cache after Reset
Nios II Device Driver Cache Considerations
Cache Considerations for Writing Program Loaders
Managing Cache in Multi-Master and Multi-Processor Systems
Nios II Tightly-Coupled Memory