Visible to Intel only — GUID: flc1481912215841
Ixiasoft
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the HPS Component Revision History
Visible to Intel only — GUID: flc1481912215841
Ixiasoft
3.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
The following tables define the HPS Conduit interfaces that connect to the FPGA.
Role Name |
Direction |
Width |
---|---|---|
h2f_pending_rst_req_n | Output |
1 |
f2h_pending_rst_ack_n | Input |
1 |
Role Name | Direction | Width |
---|---|---|
h2f_gp_in | Input | 32 |
h2f_gp_out | Output | 32 |
Role Name | Direction | Width |
---|---|---|
h2f_mpu_eventi | Input | 1 |
h2f_mpu_evento | Output | 1 |
h2f_mpu_standbywfe | Output | 4 |
h2f_mpu_standbywfi | Output | 4 |
Role Name | Direction | Width |
---|---|---|
f2h_dma_req<0-7>_req | Input | 1 |
f2h_dma_req<0-7>_single | Input | 1 |
f2h_dma_req<0-7>_ack | Output | 1 |
Role Name | Direction | Width |
---|---|---|
h2f_dbg_apb_PCLKEN | Input | 1 |
h2f_dbg_apb_DBG_APB_DISABLE | Input | 1 |
Role Name | Direction | Width |
---|---|---|
f2h_stm_hwevents | Input | 43 |
Role Name | Direction | Width |
---|---|---|
h2f_cti_trig_in | Input | 8 |
h2f_cti_trig_in_ack | Output | 8 |
h2f_cti_trig_out | Output | 8 |
h2f_cti_trig_out_ack | Input | 8 |
h2f_cti_fpga_clk_en | Input | 1 |
Role Name | Direction | Width |
---|---|---|
h2f_tpiu_clk_ctrl | Input | 1 |
h2f_tpiu_data | Output | 32 |