Scalable Switch Intel® FPGA IP for PCI Express* User Guide

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ID 683515
Date 4/26/2024
Public
Document Table of Contents x
1. Overview 2. User Guide Access Information
1. Overview
2. User Guide Access Information

1. Overview

Updated for:
Intel® Quartus® Prime Design Suite 24.1

P-Tile is an FPGA companion tile die that supports PCI Express Gen4 in Endpoint, Root Port and TLP Bypass modes. It serves as a companion tile for both Stratix® 10 DX and Agilex™ 7 devices. P-Tile natively supports Gen3 and Gen4 configurations in accordance with the PCI Express Base Specification 4.0 Rev 1.0.

F-Tile is also an FPGA companion tile die that supports PCI Express Gen4 in Endpoint, Root Port and TLP Bypass modes. It serves as a companion tile for Agilex™ 7 devices. F-Tile is the successor of P-Tile and natively supports PCI Express Gen3 and Gen4 configurations in accordance with the PCI Express Base Specification 4.0 Rev 1.0.

Alternatively, R-Tile is an FPGA companion tile die that supports PCI Express Gen5 in Endpoint, Root Port and TLP Bypass modes. R-Tile natively supports Gen3, Gen4 and Gen5 configurations. It serves as a companion tile for the Agilex™ 7 devices.

The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 32 discrete downstream ports/embedded endpoints (E-EPs). This IP supports Hot Plug capability for the downstream ports. You can use the Scalable Switch Intel® FPGA IP for PCI Express along with the corresponding PCIe Hard IP (P-Tile / F-Tile / R-Tile) in TLP Bypass mode to configure the discrete downstream ports or use the Scalable Switch Intel® FPGA IP for PCI Express to configure the embedded endpoints allowing the use of fewer PCIe physical links. The Scalable Switch Intel® FPGA IP for PCI Express implements the upstream and downstream port configuration space. The PCIe Hard IP must be used in TLP Bypass mode to implement the upstream port and downstream port.
Note: For designs that require the integration of more than 32 embedded endpoint devices, please contact Intel Premier Support and quote 14022165920.

The following three figures show Switch configurations using the Scalable Switch Intel® FPGA IP for PCI Express. In the first configuration, the Endpoints are external to the Scalable Switch Intel® FPGA IP for PCI Express (these are referred to as discrete Endpoints). In the second configuration, they are embedded in the IP. The third configuration is a mix of embedded Endpoints and discrete Endpoints.

Figure 1. Scalable Switch Intel® FPGA IP for PCI Express with Discrete EPs
Note: Supporting discrete Endpoints requires the instantiation of the Scalable Switch Intel® FPGA IP for PCI Express with Downstream switch port type for each discrete Endpoint.
Figure 2. Scalable Switch Intel® FPGA IP for PCI Express with Embedded EPs
Figure 3. Scalable Switch Intel® FPGA IP for PCI Express with a Combination of Discrete and Embedded EPs
Table 1.  Scalable Switch Intel® FPGA IP for PCI Express Support Matrix

S = Simulation, C = Compilation, T = Timing, H = Hardware

N/A = Not Supported, * = Limited Support
PCIe Tile PCIe IP Support Design Example Support Timing Support
-1 -2 -3
Stratix® 10 DX Agilex™ 7 Stratix® 10 DX Agilex™ 7 Stratix® 10 DX Agilex™ 7
P-Tile S*, C, T, H* S*, C, T, H* 400 MHz 500 MHz 400 MHz 500 MHz N/A N/A
F-Tile S*, C, T S*, C, T N/A 500 MHz N/A 500 MHz N/A N/A
R-Tile S*, C, T S*, C, T N/A 500 MHz N/A 500 MHz N/A N/A
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