Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

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ID 683506
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Power Analysis 2. Power Optimization A. Intel® Quartus® Prime Standard Edition User Guides
1. Power Analysis x
1.1. Comparison of the EPE and the Intel® Quartus® Prime Power Analyzer 1.2. Power Estimations and Design Requirements 1.3. Power Analyzer Walkthrough 1.4. Inputs for the Power Analyzer 1.5. Power Analysis in Modular Design Flows 1.6. Power Analyzer Compilation Report 1.7. Scripting Support 1.8. Power Analysis Revision History
1.4. Inputs for the Power Analyzer x
1.4.1. Operating Settings and Conditions 1.4.2. Sources for Signal Activity Data
1.4.2. Sources for Signal Activity Data x
1.4.2.1. Waveforms from Supported Simulators 1.4.2.2. .vcd Files from Third-Party Simulation Tools 1.4.2.3. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 1.4.2.4. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 1.4.2.5. Signal Activities from User Defaults Only
1.4.2.2. .vcd Files from Third-Party Simulation Tools x
1.4.2.2.1. Generating a .vcd in a EDA Simulation Tool 1.4.2.2.2. Generating a .vcd from ModelSim® Software
1.4.2.3. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation x
1.4.2.3.1. RTL Simulation Limitation
1.5. Power Analysis in Modular Design Flows x
1.5.1. Complete Design Simulation 1.5.2. Modular Design Simulation 1.5.3. Multiple Simulations on the Same Entity 1.5.4. Overlapping Simulations 1.5.5. Partial Simulations 1.5.6. Node Name Matching Considerations 1.5.7. Glitch Filtering 1.5.8. Node and Entity Assignments 1.5.9. Default Toggle Rate Assignment 1.5.10. Vectorless Estimation
1.5.5. Partial Simulations x
1.5.5.1. Specifying Start and End Time when Performing Signal-Activity Calculations using the Limit VCD Period Option
1.5.7. Glitch Filtering x
1.5.7.1. Enabling Tool Based Glitch Filtering 1.5.7.2. Enabling Glitch Filtering During Power Analysis
1.5.8. Node and Entity Assignments x
1.5.8.1. Timing Assignments to Clock Nodes
1.7. Scripting Support x
1.7.1. Running the Power Analyzer from the Command–Line
2. Power Optimization x
2.1. Factors Affecting Power Consumption 2.2. Power Dissipation 2.3. Design Space Explorer II for Power-Driven Optimization 2.4. Power-Driven Compilation 2.5. Design Guidelines 2.6. Power Optimization Advisor 2.7. Power Optimization Revision History
2.1. Factors Affecting Power Consumption x
2.1.1. Design Activity and Power Analysis 2.1.2. Device Selection 2.1.3. Environmental Conditions 2.1.4. Device Resource Usage 2.1.5. Signal Activity
2.1.4. Device Resource Usage x
2.1.4.1. Number, Type, and Loading of I/O Pins 2.1.4.2. Number and Type of Hard Logic Blocks 2.1.4.3. Number and Type of Global Signals
2.1.5. Signal Activity x
2.1.5.1. Toggle Rate 2.1.5.2. Static Probability
2.4. Power-Driven Compilation x
2.4.1. Power-Driven Synthesis 2.4.2. Power-Driven Fitter 2.4.3. Area-Driven Synthesis 2.4.4. Gate-Level Register Retiming 2.4.5. Intel® Quartus® Prime Compiler Settings 2.4.6. Assignment Editor Options
2.4.1. Power-Driven Synthesis x
2.4.1.1. Memory Block Optimization 2.4.1.2. Power-Aware Logic Mapping 2.4.1.3. Power-Aware Memory Balancing
2.5. Design Guidelines x
2.5.1. Clock Power Management 2.5.2. Pipelining and Retiming 2.5.3. Architectural Optimization 2.5.4. I/O Power Guidelines 2.5.5. Memory Optimization (M20K/MLAB) 2.5.6. DDR Memory Controller Settings 2.5.7. DSP Implementation 2.5.8. Reducing High-Speed Tile (HST) Usage 2.5.9. Unused Transceiver Channels 2.5.10. Periphery Power reduction XCVR Settings
2.5.1. Clock Power Management x
2.5.1.1. Clock Enable in Memory Blocks 2.5.1.2. LAB Clock Power 2.5.1.3. Clock Enables 2.5.1.4. Global Signals 2.5.1.5. Merge Clocks
2.5.1.1. Clock Enable in Memory Blocks x
2.5.1.1.1. Memory Power Reduction Example
2.5.1.2. LAB Clock Power x
2.5.1.2.1. LAB-Wide Clock Enable Example
2.5.1.4. Global Signals x
2.5.1.4.1. Viewing Clock Details in the Chip Planner
2.5.5. Memory Optimization (M20K/MLAB) x
2.5.5.1. Implementation 2.5.5.2. Rd/Wr Enables
2.5.10. Periphery Power reduction XCVR Settings x
2.5.10.1. Transceiver Settings 2.5.10.2. I/O Current Strength
2.6. Power Optimization Advisor x
2.6.1. Set Realistic Timing Constraints 2.6.2. Appropriate Device Family 2.6.3. Dynamic Power 2.6.4. Static Power 2.6.5. Appropriate I/O Standards 2.6.6. Use RAM Blocks 2.6.7. Shut Down RAM Blocks 2.6.8. Clock Enables on Logic 2.6.9. Pipeline Logic to Reduce Glitching
2.6.1. Set Realistic Timing Constraints x
2.6.1.1. Find Timing Information
1. Power Analysis
2. Power Optimization
A. Intel® Quartus® Prime Standard Edition User Guides

1.6. Power Analyzer Compilation Report

The Power Analyzer Compilation Report contains the following sections:

Summary

The Summary section of the report shows the estimated total thermal power consumption of your design. This includes dynamic, static, and I/O thermal power consumption. The I/O thermal power includes the total I/O power drawn from the VCCIO and VCCPD power supplies and the power drawn from VCCINT in the I/O subsystem including I/O buffers and I/O registers. The report also includes a confidence metric that reflects the overall quality of the data sources for the signal activities. For example, a Low power estimation confidence value reflects that you have provided insufficient toggle rate data, or most of the signal-activity information used for power estimation is from default or vectorless estimation settings. For more information about the input data, refer to the Power Analyzer Confidence Metric report.

Settings

The Settings section of the report shows the Power Analyzer settings information of your design, including the default input toggle rates, operating conditions, and other relevant setting information.

Simulation Files Read

The Simulation Files Read section of the report lists the simulation output file that the .vcd used for power estimation. This section also includes the file ID, file type, entity, VCD start time, VCD end time, the unknown percentage, and the toggle percentage. The unknown percentage indicates the portion of the design module unused by the simulation vectors.

Operating Conditions Used

The Operating Conditions Used section of the report shows device characteristics, voltages, temperature, and cooling solution, if any, during the power estimation. This section also shows the entered junction temperature or auto-computed junction temperature during the power analysis.

Thermal Power Dissipated by Block

The Thermal Power Dissipated by Block section of the report shows estimated thermal dynamic power and thermal static power consumption categorized by atoms. This information provides you with estimated power consumption for each atom in your design.

By default, this section does not contain any data, but you can turn on the report with the Write power dissipation by block to report file option on the Power Analyzer Settings page.

Thermal Power Dissipation by Block Type (Device Resource Type)

This Thermal Power Dissipation by Block Type (Device Resource Type) section of the report shows the estimated thermal dynamic power and thermal static power consumption categorized by block types. This information is further categorized by estimated dynamic and static power and provides an average toggle rate by block type. Thermal power is the power dissipated as heat from the FPGA device.

Thermal Power Dissipation by Hierarchy

This Thermal Power Dissipation by Hierarchy section of the report shows estimated thermal dynamic power and thermal static power consumption categorized by design hierarchy. This information is further categorized by the dynamic and static power that was used by the blocks and routing in that hierarchy. This information is useful when locating modules with high power consumption in your design.

Core Dynamic Thermal Power Dissipation by Clock Domain

The Core Dynamic Thermal Power Dissipation by Clock Domain section of the report shows the estimated total core dynamic power dissipation by each clock domain, which provides designs with estimated power consumption for each clock domain in the design. If the clock frequency for a domain is unspecified by a constraint, the clock frequency is listed as “unspecified.” For all the combinational logic, the clock domain is listed as no clock with zero MHz.

Current Drawn from Voltage Supplies

The Current Drawn from Voltage Supplies section of the report lists the current drawn from each voltage supply. The VCCIO and VCCPD voltage supplies are further categorized by I/O bank and by voltage. This section also lists the minimum safe power supply size (current supply ability) for each supply voltage. Minimum current requirement can be higher than user mode current requirement in cases in which the supply has a specific power up current requirement that goes beyond user mode requirement, such as the VCCPD power rail in Stratix® III and Stratix® IV devices, and the VCCIO power rail in Stratix® IV devices.

The I/O thermal power dissipation on the summary page does not correlate directly to the power drawn from the VCCIO and VCCPD voltage supplies listed in this report. This is because the I/O thermal power dissipation value also includes portions of the VCCINT power, such as the I/O element (IOE) registers, which are modeled as I/O power, but do not draw from the VCCIO and VCCPD supplies.

The reported current drawn from the I/O Voltage Supplies (ICCIO and ICCPD) as reported in the Power Analyzer report includes any current drawn through the I/O into off-chip termination resistors. This can result in ICCIO and ICCPD values that are higher than the reported I/O thermal power, because this off-chip current dissipates as heat elsewhere and does not factor in the calculation of device temperature. Therefore, total I/O thermal power does not equal the sum of current drawn from each VCCIO and VCCPD supply multiplied by VCCIO and VCCPD voltage.

For SoC devices or for Arria® V SoC and Cyclone® V SoC devices, there is no standalone ICC_AUX_SHARED current drawn information. The ICC_AUX_SHARED is reported together with ICC_AUX.

Confidence Metric Details

The Confidence Metric is defined in terms of the total weight of signal activity data sources for both combinational and registered signals. Each signal has two data sources allocated to it; a toggle rate source and a static probability source.

The Confidence Metric Details section also indicates the quality of the signal toggle rate data to compute a power estimate. The confidence metric is low if the signal toggle rate data comes from poor predictors of real signal toggle rates in the device during an operation. Toggle rate data that comes from simulation, user-entered assignments on specific signals or entities are reliable. Toggle rate data from default toggle rates (for example, 12.5% of the clock period) or vectorless estimation are relatively inaccurate. This section gives an overall confidence rating in the toggle rate data, from low to high. This section also summarizes how many pins, registers, and combinational nodes obtained their toggle rates from each of simulation, user entry, vectorless estimation, or default toggle rate estimations. This detailed information helps you understand how to increase the confidence metric, letting you determine your own confidence in the toggle rate data.

Signal Activities

The Signal Activities section lists toggle rates and static probabilities assumed by power analysis for all signals with fan-out and pins. This section also lists the signal type (pin, registered, or combinational) and the data source for the toggle rate and static probability. By default, this section does not contain any data, but you can turn on the report with the Write signal activities to report file option on the Power Analyzer Settings page.

Intel recommends that you keep the Write signal activities to report file option turned off for a large design because of the large number of signals present. You can use the Assignment Editor to specify that activities for individual nodes or entities are reported by assigning an on value to those nodes for the Power Report Signal Activities assignment.

Messages

The Messages section lists the messages that the Intel® Quartus® Prime software generates during the analysis.

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