Intel® Quartus® Prime Standard Edition User Guide: Power Analysis and Optimization

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ID 683506
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Power Analysis 2. Power Optimization A. Intel® Quartus® Prime Standard Edition User Guides
1. Power Analysis x
1.1. Comparison of the EPE and the Intel® Quartus® Prime Power Analyzer 1.2. Power Estimations and Design Requirements 1.3. Power Analyzer Walkthrough 1.4. Inputs for the Power Analyzer 1.5. Power Analysis in Modular Design Flows 1.6. Power Analyzer Compilation Report 1.7. Scripting Support 1.8. Power Analysis Revision History
1.4. Inputs for the Power Analyzer x
1.4.1. Operating Settings and Conditions 1.4.2. Sources for Signal Activity Data
1.4.2. Sources for Signal Activity Data x
1.4.2.1. Waveforms from Supported Simulators 1.4.2.2. .vcd Files from Third-Party Simulation Tools 1.4.2.3. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation 1.4.2.4. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities 1.4.2.5. Signal Activities from User Defaults Only
1.4.2.2. .vcd Files from Third-Party Simulation Tools x
1.4.2.2.1. Generating a .vcd in a EDA Simulation Tool 1.4.2.2.2. Generating a .vcd from ModelSim® Software
1.4.2.3. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation x
1.4.2.3.1. RTL Simulation Limitation
1.5. Power Analysis in Modular Design Flows x
1.5.1. Complete Design Simulation 1.5.2. Modular Design Simulation 1.5.3. Multiple Simulations on the Same Entity 1.5.4. Overlapping Simulations 1.5.5. Partial Simulations 1.5.6. Node Name Matching Considerations 1.5.7. Glitch Filtering 1.5.8. Node and Entity Assignments 1.5.9. Default Toggle Rate Assignment 1.5.10. Vectorless Estimation
1.5.5. Partial Simulations x
1.5.5.1. Specifying Start and End Time when Performing Signal-Activity Calculations using the Limit VCD Period Option
1.5.7. Glitch Filtering x
1.5.7.1. Enabling Tool Based Glitch Filtering 1.5.7.2. Enabling Glitch Filtering During Power Analysis
1.5.8. Node and Entity Assignments x
1.5.8.1. Timing Assignments to Clock Nodes
1.7. Scripting Support x
1.7.1. Running the Power Analyzer from the Command–Line
2. Power Optimization x
2.1. Factors Affecting Power Consumption 2.2. Power Dissipation 2.3. Design Space Explorer II for Power-Driven Optimization 2.4. Power-Driven Compilation 2.5. Design Guidelines 2.6. Power Optimization Advisor 2.7. Power Optimization Revision History
2.1. Factors Affecting Power Consumption x
2.1.1. Design Activity and Power Analysis 2.1.2. Device Selection 2.1.3. Environmental Conditions 2.1.4. Device Resource Usage 2.1.5. Signal Activity
2.1.4. Device Resource Usage x
2.1.4.1. Number, Type, and Loading of I/O Pins 2.1.4.2. Number and Type of Hard Logic Blocks 2.1.4.3. Number and Type of Global Signals
2.1.5. Signal Activity x
2.1.5.1. Toggle Rate 2.1.5.2. Static Probability
2.4. Power-Driven Compilation x
2.4.1. Power-Driven Synthesis 2.4.2. Power-Driven Fitter 2.4.3. Area-Driven Synthesis 2.4.4. Gate-Level Register Retiming 2.4.5. Intel® Quartus® Prime Compiler Settings 2.4.6. Assignment Editor Options
2.4.1. Power-Driven Synthesis x
2.4.1.1. Memory Block Optimization 2.4.1.2. Power-Aware Logic Mapping 2.4.1.3. Power-Aware Memory Balancing
2.5. Design Guidelines x
2.5.1. Clock Power Management 2.5.2. Pipelining and Retiming 2.5.3. Architectural Optimization 2.5.4. I/O Power Guidelines 2.5.5. Memory Optimization (M20K/MLAB) 2.5.6. DDR Memory Controller Settings 2.5.7. DSP Implementation 2.5.8. Reducing High-Speed Tile (HST) Usage 2.5.9. Unused Transceiver Channels 2.5.10. Periphery Power reduction XCVR Settings
2.5.1. Clock Power Management x
2.5.1.1. Clock Enable in Memory Blocks 2.5.1.2. LAB Clock Power 2.5.1.3. Clock Enables 2.5.1.4. Global Signals 2.5.1.5. Merge Clocks
2.5.1.1. Clock Enable in Memory Blocks x
2.5.1.1.1. Memory Power Reduction Example
2.5.1.2. LAB Clock Power x
2.5.1.2.1. LAB-Wide Clock Enable Example
2.5.1.4. Global Signals x
2.5.1.4.1. Viewing Clock Details in the Chip Planner
2.5.5. Memory Optimization (M20K/MLAB) x
2.5.5.1. Implementation 2.5.5.2. Rd/Wr Enables
2.5.10. Periphery Power reduction XCVR Settings x
2.5.10.1. Transceiver Settings 2.5.10.2. I/O Current Strength
2.6. Power Optimization Advisor x
2.6.1. Set Realistic Timing Constraints 2.6.2. Appropriate Device Family 2.6.3. Dynamic Power 2.6.4. Static Power 2.6.5. Appropriate I/O Standards 2.6.6. Use RAM Blocks 2.6.7. Shut Down RAM Blocks 2.6.8. Clock Enables on Logic 2.6.9. Pipeline Logic to Reduce Glitching
2.6.1. Set Realistic Timing Constraints x
2.6.1.1. Find Timing Information
1. Power Analysis
2. Power Optimization
A. Intel® Quartus® Prime Standard Edition User Guides

1.8. Power Analysis Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2018.09.24 18.1.0
  • Initial release in Intel Quartus Prime Standard Edition User Guide.
  • General chapter reorganization.
  • Moved Factors Affecting Power Consumption to chapter: Power Optimization.
  • Updated figure: Power Analyzer High-level Flow.
  • Divided topic: Types of Power Analysis into two topics: Power Estimations and Design Requirements and Design Activity and Power Analysis.
  • Updated figure: Power Analysis Tools from Design Concept through Design Implementation and renamed to: Estimation Accuracy for Different Inputs and Power Analysis Tools
2018.06.11 18.0.0
  • In Comparison of the EPE and the Intel Quartus Prime Power Analyzer, updated the data output types that the Power Analyzer supports.
  • In Comparison of the EPE and the Intel Quartus Prime Power Analyzer, added row about estimation of transceiver power for features that you enable only through dynamic reconfiguration.
  • Specified features not supported by the Power Analyzer.
2017.05.08 17.0.0 Removed references to PowerPlay name. Power analysis occurs in the Intel Quartus Prime Power Analyzer.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel Quartus Prime.
2014.12.15 14.1.0
  • Removed Signal Activities from Full Post-fit Netlist (Timing) Simulation and Signal Activities from Full Post-fit Netlist (Zero Delay) Simulation sections as these are no longer supported.
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
2014.08.18 14.0a10.0 Updated "Current Drawn from Voltage Supplies" to clarify that for SoC devices or for Arria V SoC and Cyclone V SoC devices, there is no standalone ICC_AUX_SHARED current drawn information. The ICC_AUX_SHARED is reported together with ICC_AUX.
November 2012 12.1.0
  • Updated “Types of Power Analyses” on page 8–2, and “Confidence Metric Details” on page 8–23.
  • Added “Importance of .vcd” on page 8–20, and “Avoiding Power Estimation and Hardware Measurement Mismatch” on page 8–24
June 2012 12.0.0
  • Updated “Current Drawn from Voltage Supplies” on page 8–22.
  • Added “Using the HPS Power Calculator” on page 8–7.
November 2011 10.1.1
  • Template update.
  • Minor editorial updates.
December 2010 10.1.0
  • Added links to Quartus II Help, removed redundant material.
  • Moved “Creating PowerPlay EPE Spreadsheets” to page 8–6.
  • Minor edits.
July 2010 10.0.0
  • Removed references to the Quartus II Simulator.
  • Updated Table 8–1 on page 8–6, Table 8–2 on page 8–13, and Table 8–3 on page 8–14.
  • Updated Figure 8–3 on page 8–9, Figure 8–4 on page 8–10, and Figure 8–5 on page 8–12.
November 2009 9.1.0
  • Updated “Creating PowerPlay EPE Spreadsheets” on page 8–6 and “Simulation Results” on page 8–10.
  • Added “Signal Activities from Full Post-fit Netlist (Zero Delay) Simulation” on page 8–19 and “Generating a .vcd from Full Post-fit Netlist (Zero Delay) Simulation” on page 8–21.
  • Minor changes to “Generating a .vcd from ModelSim Software” on page 8–21.
  • Updated Figure 11–8 on page 11–24.
March 2009 9.0.0
  • This chapter was chapter 11 in version 8.1.
  • Removed Figures 11-10, 11-11, 11-13, 11-14, and 11-17 from 8.1 version.
November 2008 8.1.0
  • Updated for the Quartus II software version 8.1.
  • Replaced Figure 11-3.
  • Replaced Figure 11-14.
May 2008 8.0.0
  • Updated Figure 11–5.
  • Updated “Types of Power Analyses” on page 11–5.
  • Updated “Operating Conditions” on page 11–9.
  • Updated “PowerPlay Power Analyzer Compilation Report” on page 11–31.
  • Updated “Current Drawn from Voltage Supplies” on page 11–32.
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