Intel® Quartus® Prime Standard Edition User Guide: Getting Started

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ID 683475
Date 12/16/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® Quartus® Prime Standard Edition 2. Managing Intel® Quartus® Prime Projects 3. Design Planning 4. Introduction to Intel® FPGA IP Cores 5. Migrating to Intel® Quartus® Prime Pro Edition A. Intel® Quartus® Prime Pro Edition User Guide: Getting Started Documentation Archive B. Intel® Quartus® Prime Standard Edition User Guides
1. Introduction to Intel® Quartus® Prime Standard Edition x
1.1. Selecting an Intel® Quartus® Prime Software Edition 1.2. Introduction to Intel® Quartus® Prime Standard Edition Revision History
2. Managing Intel® Quartus® Prime Projects x
2.1. Viewing Basic Project Information 2.2. Intel® Quartus® Prime Project Contents 2.3. Managing Project Settings 2.4. Managing Logic Design Files 2.5. Managing Timing Constraints 2.6. Integrating Other EDA Tools 2.7. Exporting Compilation Results 2.8. Migrating Projects Across Operating Systems 2.9. Archiving Projects 2.10. Command-Line Interface 2.11. Managing Projects Revision History
2.1. Viewing Basic Project Information x
2.1.1. Viewing Project Reports 2.1.2. Viewing Project Messages 2.1.3. Automated Problem Reports
2.1.2. Viewing Project Messages x
2.1.2.1. Suppressing Message Display
2.2. Intel® Quartus® Prime Project Contents x
2.2.1. Project File Best Practices
2.3. Managing Project Settings x
2.3.1. Specifying the Target Device or Board 2.3.2. Optimizing Project Settings
2.3.2. Optimizing Project Settings x
2.3.2.1. Optimize Settings with Design Space Explorer II 2.3.2.2. Optimize Settings with Project Revisions 2.3.2.3. Back-Annotating Compiler Assignments
2.4. Managing Logic Design Files x
2.4.1. Including Design Libraries 2.4.2. Creating a Project Copy
2.7. Exporting Compilation Results x
2.7.1. Exporting a Version-Compatible Compilation Database 2.7.2. Importing a Version-Compatible Compilation Database 2.7.3. Exporting a Design Partition 2.7.4. Clearing Compilation Results
2.8. Migrating Projects Across Operating Systems x
2.8.1. Migrating Design Files and Libraries 2.8.2. Design Library Migration Guidelines
2.8.1. Migrating Design Files and Libraries x
2.8.1.1. Use Relative Paths
2.9. Archiving Projects x
2.9.1. Manually Adding Files To Archives 2.9.2. Archiving Compilation Results 2.9.3. Archiving Projects for Service Requests 2.9.4. Using External Revision Control
2.9.4. Using External Revision Control x
2.9.4.1. Files to Include In External Revision Control
2.10. Command-Line Interface x
2.10.1. Project Revision Commands 2.10.2. Project Archive Commands 2.10.3. Project Database Commands 2.10.4. Project Library Commands
2.10.3. Project Database Commands x
2.10.3.1. Import and Export Version-Compatible Databases from a Flow Package 2.10.3.2. quartus_cdb and quartus_sh Executables to Manage Version-Compatible Databases
2.10.4. Project Library Commands x
2.10.4.1. Specify Project Libraries With SEARCH_PATH Assignment 2.10.4.2. Report Specified Project Libraries Commands 2.10.4.3. Generate Version-Compatible Database After Compilation
3. Design Planning x
3.1. Design Planning 3.2. Create a Design Specification and Test Plan 3.3. Plan for the Target Device 3.4. Plan for Intellectual Property Cores 3.5. Plan for Standard Interfaces 3.6. Plan for Device Programming 3.7. Plan for Device Power Consumption 3.8. Plan for Interface I/O Pins 3.9. Plan for other EDA Tools 3.10. Plan for On-Chip Debugging Tools 3.11. Plan HDL Coding Styles 3.12. Plan for Hierarchical and Team-Based Designs 3.13. Design Planning Revision History
3.3. Plan for the Target Device x
3.3.1. Device Migration Planning
3.8. Plan for Interface I/O Pins x
3.8.1. Simultaneous Switching Noise Analysis
3.9. Plan for other EDA Tools x
3.9.1. Third-Party Synthesis Tools 3.9.2. Third-Party Simulation Tools
3.11. Plan HDL Coding Styles x
3.11.1. Design Recommendations 3.11.2. Recommended HDL Coding Styles 3.11.3. Managing Metastability
3.12. Plan for Hierarchical and Team-Based Designs x
3.12.1. Flat Compilation without Design Partitions 3.12.2. Incremental Compilation with Design Partitions 3.12.3. Planning Design Partitions and Floorplan Location Assignments
4. Introduction to Intel® FPGA IP Cores x
4.1. IP Catalog and Parameter Editor 4.2. Installing and Licensing Intel® FPGA IP Cores 4.3. IP General Settings 4.4. Adding Your Own IP to IP Catalog 4.5. Best Practices for Intel® FPGA IP 4.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 4.7. Modifying an IP Variation 4.8. Upgrading IP Cores 4.9. Simulating Intel® FPGA IP Cores 4.10. Synthesizing IP Cores in Other EDA Tools 4.11. Instantiating IP Cores in HDL 4.12. Introduction to Intel FPGA IP Cores Revision History
4.1. IP Catalog and Parameter Editor x
4.1.1. The Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores x
4.2.1. Intel® FPGA IP Evaluation Mode
4.2.1. Intel® FPGA IP Evaluation Mode x
4.2.1.1. Intel FPGA IP Versioning 4.2.1.2. Checking the IP License Status
4.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
4.6.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
4.8. Upgrading IP Cores x
4.8.1. Upgrading IP Cores at Command-Line 4.8.2. Migrating IP Cores to a Different Device 4.8.3. Troubleshooting IP or Platform Designer System Upgrade
4.9. Simulating Intel® FPGA IP Cores x
4.9.1. Generating IP Simulation Files 4.9.2. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
4.9.2. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) x
4.9.2.1. Setting Up NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 4.9.2.2. Generating IP Functional Simulation Models ( Intel® Quartus® Prime Standard Edition)
4.11. Instantiating IP Cores in HDL x
4.11.1. Example Top-Level Verilog HDL Module 4.11.2. Example Top-Level VHDL Module
5. Migrating to Intel® Quartus® Prime Pro Edition x
5.1. Keep Pro Edition Project Files Separate 5.2. Upgrade Project Assignments and Constraints 5.3. Upgrade IP Cores and Platform Designer (Standard) Systems 5.4. Upgrade Non-Compliant Design RTL 5.5. Migrating to Intel® Quartus® Prime Pro Edition Revision History
5.2. Upgrade Project Assignments and Constraints x
5.2.1. Modify Entity Name Assignments 5.2.2. Resolve Timing Constraint Entity Names 5.2.3. Verify Generated Node Name Assignments 5.2.4. Replace Logic Lock (Standard) Regions 5.2.5. Modify Signal Tap Logic Analyzer Files 5.2.6. Remove References to .qip Files 5.2.7. Remove Unsupported Feature Assignments
5.2.4. Replace Logic Lock (Standard) Regions x
5.2.4.1. Logic Lock Region Assignment Examples
5.4. Upgrade Non-Compliant Design RTL x
5.4.1. Verify Verilog Compilation Unit 5.4.2. Update Entity Auto-Discovery 5.4.3. Ensure Distinct VHDL Namespace for Each Library 5.4.4. Remove Unsupported Parameter Passing 5.4.5. Remove Unsized Constant from WYSIWYG Instantiation 5.4.6. Remove Non-Standard Pragmas 5.4.7. Declare Objects Before Initial Values 5.4.8. Confine SystemVerilog Features to SystemVerilog Files 5.4.9. Avoid Assignment Mixing in Always Blocks 5.4.10. Avoid Unconnected, Non-Existent Ports 5.4.11. Avoid Illegal Parameter Ranges 5.4.12. Update Verilog HDL and VHDL Type Mapping
5.4.1. Verify Verilog Compilation Unit x
5.4.1.1. Verilog HDL Configuration Instantiation
1. Introduction to Intel® Quartus® Prime Standard Edition
2. Managing Intel® Quartus® Prime Projects
3. Design Planning
4. Introduction to Intel® FPGA IP Cores
5. Migrating to Intel® Quartus® Prime Pro Edition
A. Intel® Quartus® Prime Pro Edition User Guide: Getting Started Documentation Archive
B. Intel® Quartus® Prime Standard Edition User Guides

3.7. Plan for Device Power Consumption

You can use the Intel® Quartus® Prime power estimation and analysis tools to estimate power consumption and guide PCB board and system design. You must accurately estimate device power consumption to develop an appropriate power budget and to design the power supplies, voltage regulators, heat sink, and cooling system. You can use the Early Power Estimator (EPE) spreadsheet to estimate power consumption before running a compilation or creating any source code. Then, you can use the Intel® Quartus® Prime Power Analyzer to perform a more accurate analysis after your design is complete.
Note: Because power consumption is heavily dependent on actual design and environmental conditions, make sure to verify the actual power consumption during device operation.

Power estimation and analysis helps you ensure that your design satisfies thermal and power supply requirements:

  • Thermal—ensure that the cooling solution is sufficient to dissipate the heat generated by the device. The computed junction temperature must fall within normal device specifications.
  • Power supply—ensure that the power supplies provide adequate current to support device operation.

Early Power Estimator (EPE) Spreadsheet

The Early Power Estimator (EPE) spreadsheet allows you to estimate power utilization for your design. Estimating power consumption early in the design cycle allows planning of power budgets and avoids unexpected results when designing the PCB.

Figure 24. Early Power Estimator (EPE) Spreadsheet

You can manually enter data into the EPE spreadsheet, or use the Intel® Quartus® Prime software to generate device resource information for your design.

To manually enter data into the EPE spreadsheet, enter the device resources, operating frequency, toggle rates, and other parameters for your design. If you do not have an existing design, estimate the number of device resources used in your design, and then enter the data into the EPE spreadsheet manually.

If you have an existing design or a partially completed design, you can use the Intel® Quartus® Prime software to generate the Early Power Estimator File (.txt, .csv) to assist you in completing the EPE spreadsheet.

The EPE spreadsheet includes the Import Data macro that parses the information in the EPE File and transfers the information into the spreadsheet. If you do not want to use the macro, you can manually transfer the data into the EPE spreadsheet. For example, after importing the EPE File information into the EPE spreadsheet, you can add device resource information. If the existing Intel® Quartus® Prime project represents only a portion of your full design, manually enter the additional device resources you use in the final design.

Intel® Quartus® Prime Power Analyzer

After you complete your design, you can use the Intel® Quartus® Prime Power Analyzer to perform a complete post-fit power analysis to check the power consumption more accurately. The Power Analyzer provides an accurate estimation of power, ensuring that thermal and supply limitations are met.

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