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1. Introduction to Intel® Quartus® Prime Standard Edition
2. Managing Intel® Quartus® Prime Projects
3. Design Planning
4. Introduction to Intel® FPGA IP Cores
5. Migrating to Intel® Quartus® Prime Pro Edition
A. Intel® Quartus® Prime Pro Edition User Guide: Getting Started Documentation Archive
B. Intel® Quartus® Prime Standard Edition User Guides
2.1. Viewing Basic Project Information
2.2. Intel® Quartus® Prime Project Contents
2.3. Managing Project Settings
2.4. Managing Logic Design Files
2.5. Managing Timing Constraints
2.6. Integrating Other EDA Tools
2.7. Exporting Compilation Results
2.8. Migrating Projects Across Operating Systems
2.9. Archiving Projects
2.10. Command-Line Interface
2.11. Managing Projects Revision History
3.1. Design Planning
3.2. Create a Design Specification and Test Plan
3.3. Plan for the Target Device
3.4. Plan for Intellectual Property Cores
3.5. Plan for Standard Interfaces
3.6. Plan for Device Programming
3.7. Plan for Device Power Consumption
3.8. Plan for Interface I/O Pins
3.9. Plan for other EDA Tools
3.10. Plan for On-Chip Debugging Tools
3.11. Plan HDL Coding Styles
3.12. Plan for Hierarchical and Team-Based Designs
3.13. Design Planning Revision History
4.1. IP Catalog and Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores
4.3. IP General Settings
4.4. Adding Your Own IP to IP Catalog
4.5. Best Practices for Intel® FPGA IP
4.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition)
4.7. Modifying an IP Variation
4.8. Upgrading IP Cores
4.9. Simulating Intel® FPGA IP Cores
4.10. Synthesizing IP Cores in Other EDA Tools
4.11. Instantiating IP Cores in HDL
4.12. Introduction to Intel FPGA IP Cores Revision History
5.2.1. Modify Entity Name Assignments
5.2.2. Resolve Timing Constraint Entity Names
5.2.3. Verify Generated Node Name Assignments
5.2.4. Replace Logic Lock (Standard) Regions
5.2.5. Modify Signal Tap Logic Analyzer Files
5.2.6. Remove References to .qip Files
5.2.7. Remove Unsupported Feature Assignments
5.4.1. Verify Verilog Compilation Unit
5.4.2. Update Entity Auto-Discovery
5.4.3. Ensure Distinct VHDL Namespace for Each Library
5.4.4. Remove Unsupported Parameter Passing
5.4.5. Remove Unsized Constant from WYSIWYG Instantiation
5.4.6. Remove Non-Standard Pragmas
5.4.7. Declare Objects Before Initial Values
5.4.8. Confine SystemVerilog Features to SystemVerilog Files
5.4.9. Avoid Assignment Mixing in Always Blocks
5.4.10. Avoid Unconnected, Non-Existent Ports
5.4.11. Avoid Illegal Parameter Ranges
5.4.12. Update Verilog HDL and VHDL Type Mapping
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4.9.1. Generating IP Simulation Files
The Intel® Quartus® Prime software optionally generates the functional simulation model, any testbench (or example design), and vendor-specific simulator setup scripts when you generate an IP core. To control the generation of IP simulation files:
- To specify your supported simulator and options for IP simulation file generation, click Assignment > Settings > EDA Tool Settings > Simulation.
- To parameterize a new IP variation, enable generation of simulation files, and generate the IP core synthesis and simulation files, click Tools > IP Catalog.
- To edit parameters and regenerate synthesis or simulation files for an existing IP core variation, click View > Project Navigator > IP Components.
- To edit parameters and regenerate synthesis or simulation files for an existing IP core variation, click View > Utility Windows > Project Navigator > IP Components.
| File Type | Description | File Name |
|---|---|---|
| Simulator setup scripts | Vendor-specific scripts to compile, elaborate, and simulate Intel® FPGA IP models and simulation model library files.
Note: For Intel® Arria® 10 designs, you can use the Intel® Quartus® Prime software to automatically create a combined simulator setup script. Refer to Scripting IP Simulation in the Introduction to Intel® FPGA IP Cores for more information.
|
<my_dir>/aldec/riviera_setup.tcl <my_dir>/cadence/ncsim__setup.sh <my_dir>/mentor/msim_setup.tcl <my_dir>/synopsys/vcs/vcs_setup.sh <my_dir>/synopsys/vcsmx/vcsmx_setup.sh |
| Simulation IP File ( Intel® Quartus® Prime Standard Edition) | Contains IP core simulation library mapping information. To use NativeLink, add the .qip and .sip files generated for IP to your project. | <design name>.sip |
| IP functional simulation models ( Intel® Quartus® Prime Standard Edition) | IP functional simulation models are cycle-accurate VHDL or Verilog HDL models a that the Intel® Quartus® Prime software generates for some Intel FPGA IP cores. IP functional simulation models support fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators. | <my_ip>.vho <my_ip>.vo |
| IEEE encrypted models ( Intel® Quartus® Prime Standard Edition) | Intel provides Arria® V, Cyclone® V, Stratix® V, and newer simulation model libraries and IP simulation models in Verilog HDL and IEEE-encrypted Verilog HDL. Your simulator's co-simulation capabilities support VHDL simulation of these models. IEEE encrypted Verilog HDL models are significantly faster than IP functional simulation models. The Intel® Quartus® Prime Pro Edition software does not support these models. | <my_ip>.v |
Note: Intel® FPGA IP cores support a variety of cycle-accurate simulation models, including simulation-specific IP functional simulation models and encrypted RTL models, and plain text RTL models. The models support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog HDL simulators. For some IP cores, generation only produces the plain text RTL model, and you can simulate that model. Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.