Intel® Quartus® Prime Standard Edition User Guide: Getting Started

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ID 683475
Date 12/16/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® Quartus® Prime Standard Edition 2. Managing Intel® Quartus® Prime Projects 3. Design Planning 4. Introduction to Intel® FPGA IP Cores 5. Migrating to Intel® Quartus® Prime Pro Edition A. Intel® Quartus® Prime Pro Edition User Guide: Getting Started Documentation Archive B. Intel® Quartus® Prime Standard Edition User Guides
1. Introduction to Intel® Quartus® Prime Standard Edition x
1.1. Selecting an Intel® Quartus® Prime Software Edition 1.2. Introduction to Intel® Quartus® Prime Standard Edition Revision History
2. Managing Intel® Quartus® Prime Projects x
2.1. Viewing Basic Project Information 2.2. Intel® Quartus® Prime Project Contents 2.3. Managing Project Settings 2.4. Managing Logic Design Files 2.5. Managing Timing Constraints 2.6. Integrating Other EDA Tools 2.7. Exporting Compilation Results 2.8. Migrating Projects Across Operating Systems 2.9. Archiving Projects 2.10. Command-Line Interface 2.11. Managing Projects Revision History
2.1. Viewing Basic Project Information x
2.1.1. Viewing Project Reports 2.1.2. Viewing Project Messages 2.1.3. Automated Problem Reports
2.1.2. Viewing Project Messages x
2.1.2.1. Suppressing Message Display
2.2. Intel® Quartus® Prime Project Contents x
2.2.1. Project File Best Practices
2.3. Managing Project Settings x
2.3.1. Specifying the Target Device or Board 2.3.2. Optimizing Project Settings
2.3.2. Optimizing Project Settings x
2.3.2.1. Optimize Settings with Design Space Explorer II 2.3.2.2. Optimize Settings with Project Revisions 2.3.2.3. Back-Annotating Compiler Assignments
2.4. Managing Logic Design Files x
2.4.1. Including Design Libraries 2.4.2. Creating a Project Copy
2.7. Exporting Compilation Results x
2.7.1. Exporting a Version-Compatible Compilation Database 2.7.2. Importing a Version-Compatible Compilation Database 2.7.3. Exporting a Design Partition 2.7.4. Clearing Compilation Results
2.8. Migrating Projects Across Operating Systems x
2.8.1. Migrating Design Files and Libraries 2.8.2. Design Library Migration Guidelines
2.8.1. Migrating Design Files and Libraries x
2.8.1.1. Use Relative Paths
2.9. Archiving Projects x
2.9.1. Manually Adding Files To Archives 2.9.2. Archiving Compilation Results 2.9.3. Archiving Projects for Service Requests 2.9.4. Using External Revision Control
2.9.4. Using External Revision Control x
2.9.4.1. Files to Include In External Revision Control
2.10. Command-Line Interface x
2.10.1. Project Revision Commands 2.10.2. Project Archive Commands 2.10.3. Project Database Commands 2.10.4. Project Library Commands
2.10.3. Project Database Commands x
2.10.3.1. Import and Export Version-Compatible Databases from a Flow Package 2.10.3.2. quartus_cdb and quartus_sh Executables to Manage Version-Compatible Databases
2.10.4. Project Library Commands x
2.10.4.1. Specify Project Libraries With SEARCH_PATH Assignment 2.10.4.2. Report Specified Project Libraries Commands 2.10.4.3. Generate Version-Compatible Database After Compilation
3. Design Planning x
3.1. Design Planning 3.2. Create a Design Specification and Test Plan 3.3. Plan for the Target Device 3.4. Plan for Intellectual Property Cores 3.5. Plan for Standard Interfaces 3.6. Plan for Device Programming 3.7. Plan for Device Power Consumption 3.8. Plan for Interface I/O Pins 3.9. Plan for other EDA Tools 3.10. Plan for On-Chip Debugging Tools 3.11. Plan HDL Coding Styles 3.12. Plan for Hierarchical and Team-Based Designs 3.13. Design Planning Revision History
3.3. Plan for the Target Device x
3.3.1. Device Migration Planning
3.8. Plan for Interface I/O Pins x
3.8.1. Simultaneous Switching Noise Analysis
3.9. Plan for other EDA Tools x
3.9.1. Third-Party Synthesis Tools 3.9.2. Third-Party Simulation Tools
3.11. Plan HDL Coding Styles x
3.11.1. Design Recommendations 3.11.2. Recommended HDL Coding Styles 3.11.3. Managing Metastability
3.12. Plan for Hierarchical and Team-Based Designs x
3.12.1. Flat Compilation without Design Partitions 3.12.2. Incremental Compilation with Design Partitions 3.12.3. Planning Design Partitions and Floorplan Location Assignments
4. Introduction to Intel® FPGA IP Cores x
4.1. IP Catalog and Parameter Editor 4.2. Installing and Licensing Intel® FPGA IP Cores 4.3. IP General Settings 4.4. Adding Your Own IP to IP Catalog 4.5. Best Practices for Intel® FPGA IP 4.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 4.7. Modifying an IP Variation 4.8. Upgrading IP Cores 4.9. Simulating Intel® FPGA IP Cores 4.10. Synthesizing IP Cores in Other EDA Tools 4.11. Instantiating IP Cores in HDL 4.12. Introduction to Intel FPGA IP Cores Revision History
4.1. IP Catalog and Parameter Editor x
4.1.1. The Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores x
4.2.1. Intel® FPGA IP Evaluation Mode
4.2.1. Intel® FPGA IP Evaluation Mode x
4.2.1.1. Intel FPGA IP Versioning 4.2.1.2. Checking the IP License Status
4.6. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
4.6.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
4.8. Upgrading IP Cores x
4.8.1. Upgrading IP Cores at Command-Line 4.8.2. Migrating IP Cores to a Different Device 4.8.3. Troubleshooting IP or Platform Designer System Upgrade
4.9. Simulating Intel® FPGA IP Cores x
4.9.1. Generating IP Simulation Files 4.9.2. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition)
4.9.2. Using NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) x
4.9.2.1. Setting Up NativeLink Simulation ( Intel® Quartus® Prime Standard Edition) 4.9.2.2. Generating IP Functional Simulation Models ( Intel® Quartus® Prime Standard Edition)
4.11. Instantiating IP Cores in HDL x
4.11.1. Example Top-Level Verilog HDL Module 4.11.2. Example Top-Level VHDL Module
5. Migrating to Intel® Quartus® Prime Pro Edition x
5.1. Keep Pro Edition Project Files Separate 5.2. Upgrade Project Assignments and Constraints 5.3. Upgrade IP Cores and Platform Designer (Standard) Systems 5.4. Upgrade Non-Compliant Design RTL 5.5. Migrating to Intel® Quartus® Prime Pro Edition Revision History
5.2. Upgrade Project Assignments and Constraints x
5.2.1. Modify Entity Name Assignments 5.2.2. Resolve Timing Constraint Entity Names 5.2.3. Verify Generated Node Name Assignments 5.2.4. Replace Logic Lock (Standard) Regions 5.2.5. Modify Signal Tap Logic Analyzer Files 5.2.6. Remove References to .qip Files 5.2.7. Remove Unsupported Feature Assignments
5.2.4. Replace Logic Lock (Standard) Regions x
5.2.4.1. Logic Lock Region Assignment Examples
5.4. Upgrade Non-Compliant Design RTL x
5.4.1. Verify Verilog Compilation Unit 5.4.2. Update Entity Auto-Discovery 5.4.3. Ensure Distinct VHDL Namespace for Each Library 5.4.4. Remove Unsupported Parameter Passing 5.4.5. Remove Unsized Constant from WYSIWYG Instantiation 5.4.6. Remove Non-Standard Pragmas 5.4.7. Declare Objects Before Initial Values 5.4.8. Confine SystemVerilog Features to SystemVerilog Files 5.4.9. Avoid Assignment Mixing in Always Blocks 5.4.10. Avoid Unconnected, Non-Existent Ports 5.4.11. Avoid Illegal Parameter Ranges 5.4.12. Update Verilog HDL and VHDL Type Mapping
5.4.1. Verify Verilog Compilation Unit x
5.4.1.1. Verilog HDL Configuration Instantiation
1. Introduction to Intel® Quartus® Prime Standard Edition
2. Managing Intel® Quartus® Prime Projects
3. Design Planning
4. Introduction to Intel® FPGA IP Cores
5. Migrating to Intel® Quartus® Prime Pro Edition
A. Intel® Quartus® Prime Pro Edition User Guide: Getting Started Documentation Archive
B. Intel® Quartus® Prime Standard Edition User Guides

1. Introduction to Intel® Quartus® Prime Standard Edition

Updated for:
Intel® Quartus® Prime Design Suite 19.4
This document is part of a collection. You can download the entire collection as a single PDF: Intel® Quartus® Prime Standard Edition User Guides - Combined PDF link

This user guide describes basic concepts and operation of the Intel® Quartus® Prime Standard Edition design software, including GUI and project structure basics, initial design planning, use of Intel FPGA IP, and migration to Intel® Quartus® Prime Pro Edition. The Intel® Quartus® Prime Standard Edition software provides a complete design environment for the following device families:

  • Intel® Arria® 10, Arria® V, and Arria® II
  • Intel® Cyclone® 10 LP, Cyclone IV, and Cyclone V
  • MAX® series

The Intel® Quartus® Prime software GUI supports easy design entry, fast design processing, straightforward device programming, and integration with other industry-standard EDA tools. The user interface makes it easy for you to focus on your design—not on the design tool. The modular Compiler streamlines the FPGA development process, and ensures the highest performance for the least effort.

Figure 1.  Intel® Quartus® Prime Standard Edition Software GUI

The Intel® Quartus® Prime Standard Edition software offers a full range of features at each phase of the design flow to shorten your design cycle and achieve the highest performance:

  • Easy Project Setup—quickly create a new project, add design files, and specify the target Intel® device with the New Project Wizard. Create different revisions of your project to compare results with different settings. Save the current state of your project and project files as a single, compressed file. Refer to Managing Intel Quartus Prime Projects for more information.
  • Design Planning Tools— plan for initial I/O pin layout, power consumption, and area utilization in the Early Power Estimator, the Power Analyzer Tool, and the Pin Planner. Refer to Design Planning for more information.
  • Design Constraint Entry—specify timing, placement, and other constraints with the Settings dialog box, Assignment Editor, Pin Planner, and Timing Analyzer. Visualize and modify logic placement within a view of the device floorplan in the Chip Planner and Timing Closure Floorplan. Refer to Intel Quartus Prime Standard Edition User Guide: Design Constraints for more information.
  • Integrated Synthesis—provides efficient synthesis support for VHDL (1987, 1993, 2008), Verilog HDL (1995, 2001), and SystemVerilog (2005) design entry languages. Refer to Intel Quartus Prime Standard Edition User Guide: Compiler for more information.
  • Incremental Compilation—preserve the results and performance for unchanged logic in your design as you make changes elsewhere, facilitating top-down or bottom-up team-based design methodologies. Refer to Intel Quartus Prime Standard Edition User Guide: Compiler for more information.
  • Optimizing Results—Design Space Explorer automatically determines the best combination of settings for your design. Design Assistant validates your project against predetermined design rules for gated clocks, reset signals, asynchronous design practices, and signal race conditions. Refer to Intel Quartus Prime Standard Edition User Guide: Design Optimization for more information.
  • Design Debugging—The Signal Tap logic analyzer captures and displays real-time signal behavior in an FPGA design, allowing to examine the behavior of internal signals during normal device operation without the need for extra I/O pins or external lab equipment. The Transceiver Toolkit provides real-time control, monitoring, and debugging of the transceiver links running on your board. Refer to Intel Quartus Prime Standard Edition User Guide: Debug Tools for more information.
  • System and IP Integration—define and generate a complete system in much less time than using traditional, manual integration methods with Platform Designer (Standard). Refer to Introduction to Intel FPGA IP Cores and Intel Quartus Prime Standard Edition User Guide: Platform Designer for more information.
  • Third-party EDA Tool Support—integrate with supported versions of third-party EDA synthesis, simulation, and board-level timing analysis tools. Refer to Third-Party Simulation and Third-Party Synthesis user guides for more information.

The Intel® Quartus® Prime Pro Edition software expands on these capabilities of the Intel® Quartus® Prime Standard Edition, and provides unique features that support the latest Intel® FPGAs. Select the Intel® Quartus® Prime software edition that provides the device support and features you require, as Selecting an Intel Quartus Prime Software Edition describes.


Section Content
Selecting an Intel Quartus Prime Software Edition
Introduction to Intel Quartus Prime Standard Edition Revision History

Level Two Title