Arria® 10 or Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 9/10/2024
Public
Document Table of Contents

5.1.8.4. Write Descriptor Table Avalon-MM Slave Interface

This interface is available when you select the internal Descriptor Controller. This interface receives the Write DMA descriptors which are fetched by Read Data Mover. Connect the interface to the Read DMA Avalon-MM master interface.

Table 45.  Write Descriptor Table Avalon-MM Slave Interface

Signal Name

Direction

Description

WrDTSAddress_i[7:0]

Input

Specifies the descriptor table address.

WrDTSBurstCount_i[4:0]

Input

Specifies the burst count of the transaction in words.

WrDTSChipSelect_i

Input

When asserted, indicates that the write is for this slave interface.

WrDTSWaitRequest_o

Output

When asserted, indicates that this interface is busy and is not ready to respond.

WrDTSWriteData_i[255:0] or [127:0]

Input

Drives the descriptor table entry data.

WrDTSWrite_i

Input

When asserted, indicates a write transaction.