Visible to Intel only — GUID: nik1410905454726
Ixiasoft
Visible to Intel only — GUID: nik1410905454726
Ixiasoft
5.1.8.2. Write Descriptor Controller Avalon-MM Master Interface
The Avalon-MM Descriptor Controller Master interface is a 32-bit single-DWORD master with wait request support. The Write Descriptor Controller uses this interface to write status back to the PCI-Express domain and possibly MSI when MSI messages are enabled. This Avalon-MM master interface is only available for the internally instantiated Descriptor Controller.
By default MSI interrupts are enabled. You specify the Number of MSI messages requested on the MSI tab of the parameter editor. The MSI Capability Structure is defined in Section 6.8.1 MSI Capability Structure of the PCI Local Bus Specification.
Signal Name |
Direction |
Description |
---|---|---|
WrDCMAddress_o[63:0] |
Output |
Specifies the descriptor status table or MSI address. |
WrDCMByteEnable_o[3:0] |
Output |
Specifies which data bytes are valid. |
WrDCMReadDataValid_i |
Input |
When asserted, indicates that the read data is valid. |
WrRdDCMReadData_i[31:0] |
Output |
Specifies the read data for the descriptor status table entry addressed. |
WrDCMRead_o |
Output |
When asserted, indicates a read transaction. |
WrDCMWaitRequest_i |
Input |
When asserted, indicates that the Avalon-MM slave device is not ready to respond. |
WrDCMWriteData_o[31:0] |
Output |
Specifies the descriptor status table or MSI address. |
WrDCMWrite_o |
Output |
When asserted, indicates a write transaction. |