Visible to Intel only — GUID: nik1410905294432
Ixiasoft
Visible to Intel only — GUID: nik1410905294432
Ixiasoft
1.8. Resource Utilization
Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no ALMs and no embedded memory).
The Avalon-MM with DMA Arria® 10 or Cyclone® 10 GX variants include an Avalon-MM DMA bridge implemented in soft logic that operates as a front end to the hardened protocol stack. The following table shows the typical expected device resource utilization for selected configurations using the current version of the Quartus® Prime software targeting an Arria® 10 or Cyclone® 10 GX device. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.
Data Rate, Number of Lanes, and Interface Width |
ALMs |
M20K Memory Blocks |
Logic Registers |
---|---|---|---|
Gen2 x4 128 | 4300 | 29 | 5800 |
Gen2 x8 128 |
12700 |
19 |
22300 |
Gen3 x8 256 |
18000 |
47 |
31450 |