Arria® 10 or Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

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ID 683425
Date 9/10/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM DMA 3. Parameter Settings 4. Physical Layout 5. IP Core Interfaces 6. Registers 7. Reset and Clocks 8. Error Handling 9. PCI Express Protocol Stack 10. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA for PCI Express 11. Design Implementation A. Transaction Layer Packet (TLP) Header Formats B. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe Solutions User Guide Archive C. Document Revision History
1. Datasheet x
1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe* Datasheet 1.2. Features 1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces 1.4. Release Information 1.5. Device Family Support 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM DMA x
2.1. Understanding the Avalon-MM DMA Ports 2.2. Generating the Testbench 2.3. Simulating the Example Design in ModelSim* 2.4. Running a Gate-Level Simulation 2.5. Generating Synthesis Files 2.6. Compiling the Design 2.7. Creating a Quartus® Prime Project
2.2. Generating the Testbench x
2.2.1. Understanding the Simulation Generated Files 2.2.2. Understanding Simulation Log File Generation
3. Parameter Settings x
3.1. Parameters 3.2. Arria® 10 or Cyclone® 10 GX Avalon-MM Settings 3.3. Base Address Register (BAR) Settings 3.4. Device Identification Registers 3.5. PCI Express and PCI Capabilities Parameters 3.6. Configuration, Debug, and Extension Options 3.7. PHY Characteristics 3.8. Example Designs
3.1. Parameters x
3.1.1. RX Buffer Allocation Selections Available by Interface Type
3.5. PCI Express and PCI Capabilities Parameters x
3.5.1. Device Capabilities 3.5.2. Error Reporting 3.5.3. Link Capabilities 3.5.4. MSI and MSI-X Capabilities 3.5.5. Slot Capabilities 3.5.6. Power Management 3.5.7. Vendor Specific Extended Capability (VSEC)
4. Physical Layout x
4.1. Hard IP Block Placement In Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. IP Core Interfaces x
5.1. Arria® 10 or Cyclone® 10 GX DMA Avalon-MM DMA Interface to the Application Layer 5.2. Clock Signals 5.3. Reset, Status, and Link Training Signals 5.4. MSI Interrupts for Endpoints 5.5. Hard IP Reconfiguration Interface 5.6. Physical Layer Interface Signals 5.7. Test Signals 5.8. Arria® 10 Development Kit Conduit Interface
5.1. Arria® 10 or Cyclone® 10 GX DMA Avalon-MM DMA Interface to the Application Layer x
5.1.1. Avalon-MM DMA Interfaces when Descriptor Controller Is Internally Instantiated 5.1.2. Read Data Mover 5.1.3. Write DMA Avalon-MM Master Port 5.1.4. RX Master Module 5.1.5. Non-Bursing Slave Module 5.1.6. 32-Bit Control Register Access (CRA) Slave Signals 5.1.7. Avalon-ST Descriptor Control Interface when Instantiated Separately 5.1.8. Descriptor Controller Interfaces when Instantiated Internally
5.1.7. Avalon-ST Descriptor Control Interface when Instantiated Separately x
5.1.7.1. Avalon-ST Descriptor Status Interface 5.1.7.2. Avalon® -ST Descriptor Status Sources
5.1.8. Descriptor Controller Interfaces when Instantiated Internally x
5.1.8.1. Read Descriptor Controller Avalon-MM Master interface 5.1.8.2. Write Descriptor Controller Avalon-MM Master Interface 5.1.8.3. Read Descriptor Table Avalon-MM Slave Interface 5.1.8.4. Write Descriptor Table Avalon-MM Slave Interface
5.6. Physical Layer Interface Signals x
5.6.1. Serial Data Signals 5.6.2. PIPE Interface Signals
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. Advanced Error Reporting Capability 6.7. DMA Descriptor Controller Registers 6.8. Control Register Access (CRA) Avalon-MM Slave Port
6.5. Intel-Defined VSEC Registers x
6.5.1. CvP Registers
6.6. Advanced Error Reporting Capability x
6.6.1. Uncorrectable Internal Error Mask Register 6.6.2. Uncorrectable Internal Error Status Register 6.6.3. Correctable Internal Error Mask Register 6.6.4. Correctable Internal Error Status Register
6.7. DMA Descriptor Controller Registers x
6.7.1. Read DMA Descriptor Controller Registers 6.7.2. Write DMA Descriptor Controller Registers 6.7.3. Read DMA and Write DMA Descriptor Format 6.7.4. Read DMA Example 6.7.5. Software Program for Simultaneous Read and Write DMA
7. Reset and Clocks x
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 7.2. Clocks
7.2. Clocks x
7.2.1. Clock Domains 7.2.2. Clock Summary
7.2.1. Clock Domains x
7.2.1.1. coreclkout_hip 7.2.1.2. pld_clk
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
9. PCI Express Protocol Stack x
9.1. Top-Level Interfaces 9.2. Data Link Layer 9.3. Physical Layer
9.1. Top-Level Interfaces x
9.1.1. Avalon-MM DMA Interface 9.1.2. Clocks and Reset 9.1.3. Interrupts 9.1.4. PIPE
10. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA for PCI Express x
10.1. Understanding the Internal DMA Descriptor Controller 10.2. Understanding the External DMA Descriptor Controller
11. Design Implementation x
11.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 11.2. Recommended Reset Sequence to Avoid Link Training Issues 11.3. SDC Timing Constraints 11.4. Warnings Encountered When Using Narrow Avalon-MM Interfaces
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
C. Document Revision History x
C.1. Document Revision History for the Arria® 10 or Cyclone® 10 GX Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Physical Layout
5. IP Core Interfaces
6. Registers
7. Reset and Clocks
8. Error Handling
9. PCI Express Protocol Stack
10. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA for PCI Express
11. Design Implementation
A. Transaction Layer Packet (TLP) Header Formats
B. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe Solutions User Guide Archive
C. Document Revision History

5.6.2. PIPE Interface Signals

These PIPE signals are available for Gen1, Gen2, and Gen3 variants so that you can simulate using either the serial or the PIPE interface. Note that Arria® 10 and Cyclone® 10 GX devices do not support the Gen3 PIPE interface. Simulation is faster using the PIPE interface because the PIPE simulation bypasses the SERDES model. By default, the PIPE interface is 8 bits for Gen1 and Gen2 and 32 bits for Gen3. You can use the PIPE interface for simulation even though your actual design includes a serial interface to the internal transceivers. However, it is not possible to use the Hard IP PIPE interface in hardware, including probing these signals using Signal Tap Embedded Logic Analyzer. These signals are not top-level signals of the Hard IP. They are listed here to assist in debugging link training issues.

Note: The Intel Root Port BFM bypasses Gen3 Phase 2 and Phase 3 Equalization. However, Gen3 variants can perform Phase 2 and Phase 3 equalization if instructed by a third-party BFM.
Table 52.  PIPE Interface Signals In the following table, signals that include lane number 0 also exist for lanes 1-7. These signals are for simulation only. For Quartus® Prime software compilation, these pipe signals can be left floating. In Platform Designer, the signals that are part of the PIPE interface have the prefix, hip_pipe. The signals which are included to simulate the PIPE interface have the prefix, hip_pipe_sim_pipe

Signal

Direction

Description

currentcoeff0[17:0]

Output

For Gen3, indicates the coefficients to be used by the transmitter. The 18 bits specify the following coefficients:

  • [5:0]: C-1
  • [11:6]: C0
  • [17:12]: C+1
currentrxpreset0[2:0]

Output

For Gen3 designs, specifies the current preset.
eidleinfersel0[2:0]

Output

Electrical idle entry inference mechanism selection. The following encodings are defined:

  • 3'b0xx: Electrical Idle Inference not required in current LTSSM state
  • 3'b100: Absence of COM/SKP Ordered Set the in 128 us window for Gen1 or Gen2
  • 3'b101: Absence of TS1/TS2 Ordered Set in a 1280 UI interval for Gen1 or Gen2
  • 3'b110: Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and 16000 UI interval for Gen2
  • 3'b111: Absence of Electrical idle exit in 128 us window for Gen1

phystatus0

Input

PHY status <n>. This signal communicates completion of several PHY requests.

powerdown0[1:0]

Output

Power down <n>. This signal requests the PHY to change its power state to the specified state (P0, P0s, P1, or P2).

rate[1:0]

Output

Controls the link signaling rate. The following encodings are defined:
  • 2'b00: Gen1
  • 2'b01: Gen2
  • 2'b10: Gen3
  • 2'b11: Reserved
rxblkst0

Input

For Gen3 operation, indicates the start of a block in the receive direction.

rxdata0[31:0]

Input

Receive data. This bus receives data on lane <n>.

rxdatak0[3:0]

Input

Data/Control bits for the symbols of receive data. Bit 0 corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only.

rxelecidle0

Input

Receive electrical idle <n>. When asserted, indicates detection of an electrical idle.

rxpolarity0

Output

Receive polarity <n>. This signal instructs the PHY layer to invert the polarity of the 8B/10B receiver decoding block.

rxstatus0[2:0]

Input

Receive status <n>. This signal encodes receive status and error codes for the receive data stream and receiver detection.

rxvalid0

Input

Receive valid <n>. This symbol indicates symbol lock and valid data on rxdata <n> and rxdatak <n>.

sim_pipe_ltssmstate0[4:0]

Input and Output

LTSSM state: The LTSSM state machine encoding defines the following states:

  • 5’b00000: Detect.Quiet
  • 5’b 00001: Detect.Active
  • 5’b00010: Polling.Active
  • 5’b 00011: Polling.Compliance
  • 5’b 00100: Polling.Configuration
  • 5’b00101: Polling.Speed
  • 5’b00110: Config.LinkwidthsStart
  • 5’b 00111: Config.Linkaccept
  • 5’b 01000: Config.Lanenumaccept
  • 5’b01001: Config.Lanenumwait
  • 5’b01010: Config.Complete
  • 5’b 01011: Config.Idle
  • 5’b01100: Recovery.Rcvlock
  • 5’b01101: Recovery.Rcvconfig
  • 5’b01110: Recovery.Idle
  • 5’b 01111: L0
  • 5’b10000: Disable
  • 5’b10001: Loopback.Entry
  • 5’b10010: Loopback.Active
  • 5’b10011: Loopback.Exit
  • 5’b10100: Hot.Reset
  • 5’b10101: L0s
  • 5’b11001: L2.transmit.Wake
  • 5’b11010: Recovery.Speed
  • 5’b11011: Recovery.Equalization, Phase 0
  • 5’b11100: Recovery.Equalization, Phase 1
  • 5’b11101: Recovery.Equalization, Phase 2
  • 5’b11110: Recovery.Equalization, Phase 3
  • 5’b11111: Recovery.Equalization, Done
sim_pipe_pclk_in

Input

This clock is used for PIPE simulation only, and is derived from the refclk. It is the PIPE interface clock used for PIPE mode simulation.

sim_pipe_rate[1:0]

Input

Specifies the data rate. The 2-bit encodings have the following meanings:

  • 2’b00: Gen1 rate (2.5 Gbps)
  • 2’b01: Gen2 rate (5.0 Gbps)
  • 2’b1X: Gen3 rate (8.0 Gbps)

txblkst

For Gen3 operation, indicates the start of a block in the transmit direction.

txcompl0

Output

Transmit compliance <n>. This signal forces the running disparity to negative in compliance mode (negative COM character).

txdata0[31:0]

Output

Transmit data. This bus transmits data on lane <n>.

txdatak0[3:0]

Output

Transmit data control <n>. This signal serves as the control bit for txdata <n>. Bit 0 corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only.

txdataskip0

Output

For Gen3 operation. Allows the MAC to instruct the TX interface to ignore the TX data interface for one clock cycle. The following encodings are defined:

  • 1’b0: TX data is invalid
  • 1’b1: TX data is valid
txdeemph0

Output

Transmit de-emphasis selection. The value for this signal is set based on the indication received from the other end of the link during the Training Sequences (TS). You do not need to change this value.

txdetectrx0

Output

Transmit detect receive <n>. This signal tells the PHY layer to start a receive detection operation or to begin loopback.

txelecidle0

Output

Transmit electrical idle <n>. This signal forces the TX output to electrical idle.

txmargin0[2:0]

Output

Transmit VOD margin selection. The value for this signal is based on the value from the Link Control 2 Register. Available for simulation only.

txswing0

Output

When asserted, indicates full swing for the transmitter voltage. When deasserted indicates half swing.

txsynchd0 [1:0]

Output

For Gen3 operation, specifies the block type. The following encodings are defined:

  • 2'b01: Ordered Set Block
  • 2'b10: Data Block
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