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1. Datasheet
2. Getting Started with the Avalon-MM DMA
3. Parameter Settings
4. Physical Layout
5. IP Core Interfaces
6. Registers
7. Reset and Clocks
8. Error Handling
9. PCI Express Protocol Stack
10. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA for PCI Express
11. Design Implementation
A. Transaction Layer Packet (TLP) Header Formats
B. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe Solutions User Guide Archive
C. Document Revision History
1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe* Datasheet
1.2. Features
1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces
1.4. Release Information
1.5. Device Family Support
1.6. Design Examples
1.7. IP Core Verification
1.8. Resource Utilization
1.9. Recommended Speed Grades
1.10. Creating a Design for PCI Express
5.1. Arria® 10 or Cyclone® 10 GX DMA Avalon-MM DMA Interface to the Application Layer
5.2. Clock Signals
5.3. Reset, Status, and Link Training Signals
5.4. MSI Interrupts for Endpoints
5.5. Hard IP Reconfiguration Interface
5.6. Physical Layer Interface Signals
5.7. Test Signals
5.8. Arria® 10 Development Kit Conduit Interface
5.1.1. Avalon-MM DMA Interfaces when Descriptor Controller Is Internally Instantiated
5.1.2. Read Data Mover
5.1.3. Write DMA Avalon-MM Master Port
5.1.4. RX Master Module
5.1.5. Non-Bursing Slave Module
5.1.6. 32-Bit Control Register Access (CRA) Slave Signals
5.1.7. Avalon-ST Descriptor Control Interface when Instantiated Separately
5.1.8. Descriptor Controller Interfaces when Instantiated Internally
6.1. Correspondence between Configuration Space Registers and the PCIe Specification
6.2. Type 0 Configuration Space Registers
6.3. Type 1 Configuration Space Registers
6.4. PCI Express Capability Structures
6.5. Intel-Defined VSEC Registers
6.6. Advanced Error Reporting Capability
6.7. DMA Descriptor Controller Registers
6.8. Control Register Access (CRA) Avalon-MM Slave Port
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1.2. Features
New features in the Quartus® Prime 18.0 software release:
- Added support for Cyclone® 10 GX devices for up to Gen2 x4 configurations.
- Added optional parameter to invert the RX polarity.
The Arria® 10 or Cyclone® 10 GX Avalon-MM DMA for PCI Express supports the following features:
- Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
- Native support for Gen1 x8, Gen2 x4, Gen2 x8, Gen3 x2, Gen3 x4, Gen3 x8 for Endpoints for Arria® 10 devices. The variant downtrains when plugged into a lesser link width or a system which supports a lower maximum link rate.
- Native support for Gen2 x4 for Endpoints for Cyclone® 10 GX devices. The variant downtrains when plugged into a lesser link width or a system which supports a lower maximum link rate.
- Dedicated 16 KB receive buffer.
- Support for 128- or 256-bit Avalon-MM interface to Application Layer with embedded DMA up to Gen3 ×8 data rate for Arria® 10.
- Support for 128-bit Avalon-MM interface to Application Layer with embedded DMA for Gen2 x4 for Cyclone® 10 GX devices.
- Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.
- Platform Designer design example demonstrating parameterization, design modules, and connectivity.
- Extended credit allocation settings to better optimize the RX buffer space based on application type.
- Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.
- Support for Separate Reference Clock No Spread Spectrum (SRNS) architecture. The Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture is not supported.
- Easy to use:
- Flexible configuration.
- No license requirement.
- Design examples to get started.
Feature | 128-Bit Interface | 256-Bit Interface 1 |
---|---|---|
Gen1 | x8 | Not supported |
Gen2 | x4, x8 | x8 |
Gen3 2 | x2, x4 | x4, x8 |
Root Port | Not Supported | Not Supported |
Tags supported | 16 | 16 or 256 |
Maximum descriptor size | 1 MB | 1 MB |
Maximum payload size | 128 or 256 | 128 or 256 |
Immediate write3 | Not supported | Supported |
Note: Cyclone® 10 GX devices support all the features in the table above, with the exception that they only support link width and speed combinations up to Gen2 x4.
1 Cyclone® 10 GX devices only support up to the Gen2 x4 configuration.
2 Cyclone® 10 GX devices do not support Gen3 configurations.
3 The Immediate Write provides a fast mechanism to send a Write TLP upstream. The descriptor stores the 32-bit payload, replacing the Source Low Address field of the descriptor.