Arria® 10 or Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 9/10/2024
Public
Document Table of Contents

3.8. Example Designs

Table 30.  Example Designs

Parameter

Value

Description

Available Example Designs

DMA

PIO

When you select the DMA option, the generated example design includes a direct memory access application. This application includes upstream and downstream transactions.

When you select the PIO option, the generated design includes a target application including only downstream transactions.

Simulation On/Off When On, the generated output includes a simulation model.
Synthesis On/Off When On, the generated output includes a synthesis model.
Generated HDL format

Verilog/VHDL

Verilog HDL and VHDL are supported

Select Board

Arria® 10 FPGA GX Development Kit

Arria® 10 FPGA GX Development Kit ES2

None

Specifies the Arria® 10 development kit.

Select None to download to a custom board.

Note: Currently, you cannot target an Cyclone® 10 GX Development Kit when generating an example design.