C.1. Document Revision History for the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory Mapped (Avalon-MM) DMA Interface for PCIe* Solutions User Guide
Date |
Version |
Changes Made |
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2021.06.03 | 18.0.1 | Mentioned in the Features section that this IP supports the Separate Reference Clock No Spread Spectrum (SRNS) architecture and not the Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture. |
2019.12.23 | 18.0.1 | Changed the name of the 1A state of the ltssmstate signals to Recovery.Speed to follow the PCIe Specifications. |
2019.05.23 | 18.0.1 | Added a note clarifying that the 24-bit Class Code register is divided into three 8-bit fields: Base Class Code, Sub-Class Code and Programming Interface. |
2019.04.30 | 18.0.1 | Updated Table 3 to show that the Avalon-MM DMA feature is not supported in Root Port mode. |
2018.08.28 | 18.0.1 | Added the step to invoke vsim to the instructions for simulating the example design in ModelSim. |
2018.06.15 | 18.0.1 | Added note that Flush reads are not supported when burst mode for BAR2 is enabled. Updated the list of configurations supported by the Avalon-MM and Avalon-MM with DMA variants. |
2018.05.07 | 18.0 | Changed all references to Intel® Cyclone® 10 to Intel® Cyclone® 10 GX. |
2017.10.06 | 17.1 | Made the following change to the user guide:
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2017.05.26 | 17.0 | Made the following changes to the user guide:
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2017.05.08 | 17.0 | Made the following changes to the IP core:
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2017.03.15 | 16.1.1 | Made the following changes:
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2016.10.28 | 16.1 | Made the following to the IP core changes:
Made the following changes to the user guide:
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2016.05.02 | 16.0 | Redesigned the 128-bit interface to the Application Layer resulting in consistently high throughput, for both on-chip and external memory. In the Getting Started with the Avalon-MM DMA Endpoint chapter, changed the instructions to use specify the 10AX115S2F45I1SG device which is used on the Intel® Arria® 10 GX FPGA Development Kit - Production (not ES2) Edition. Added support for Intel FPGA IP Evaluation Mode in the Quartus® Prime Pro Edition software. Added simulation support for Gen3 PIPE mode using the ModelSim, VCS, and NCSim simulators. Added automatic generation of basic Signal Tap Logic Analyzer files to facilitate debugging. Revised discussion of the DMA Descriptor Controller in the Avalon-MM with DMA IP Core Architecture. Revised Read DMA Example to reflect current maximum transfer size of 64 KB for 256-bit interface. The example now corresponds to an example design provided in the <install_dir> Updated figures in Physical Layout of Hard IP in Intel® Arria® 10 Devices to include more detail about transceiver banks and channel restrictions. Added Vendor Specific Extended Capability (VSEC) Revision and User Device or Board Type ID register from the Vendor Specific Extended Capability: to the VSEC tab of the component GUI. Removed Intel® Arria® 10 PCI Express Quick Start Guide chapter. This chapter does not provide DMA functionality. Corrected description of Write Descriptor Table Avalon-MM Slave Port. Added Vendor Specific Extended Capability (VSEC) parameter descriptions which were missing from previous versions. Added transceiver bank usage placement restrictions for Gen3 ES3 devices. Removed support for -3 speed grade devices. Added appendix listing previous versions of this user guide. Corrected minor errors and typos. |
2015.11.02 | 15.1 | Made the following changes:
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2015.06.05 | 15.0 | Added note inPhysical Layout of Hard IP in Intel® Arria® 10 Devices to explain Intel® Arria® 10 design constraint that requires that if the lower HIP on one side of the device is configured with a Gen3 x4 or Gen3 x8 IP core, and the upper HIP on the same side of the device is also configured with a Gen3 IP core, then the upper HIP must be configured with a x4 or x8 IP core. |
2015.05.14 | 15.0 | Made the following changes to the user guide:
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2015.05.04 | 15.0 |
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2014.12.15 | 14.1 | Made the following changes to the Intel® Arria® 10 user guide:
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2014.08.18 | 13.1 Intel® Arria® 10 | Made the following changes to the Intel® Arria® 10 Avalon-MM DMA for PCI Express IP core:
Made the following changes to the user guide:
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2013.12.02 | 13.1 Intel® Arria® 10 | Initial release. |