Visible to Intel only — GUID: nik1410905368969
Ixiasoft
Visible to Intel only — GUID: nik1410905368969
Ixiasoft
3.5.1. Device Capabilities
Parameter |
Possible Values |
Default Value |
Description |
---|---|---|---|
Maximum payload size |
128 bytes 256 bytes 512 bytes 1024 bytes 2048 bytes |
128 bytes |
Specifies the maximum payload size supported. This parameter sets the read-only value of the max payload size supported field of the Device Capabilities register (0x084[2:0]). Address: 0x084. The Maximum payload size is 256 Bytes for the Avalon-MM interface and for the Avalon-MM with DMA interface. |
Completion timeout range |
ABCD BCD ABC AB B A None |
ABCD |
Indicates device function support for the optional completion timeout programmability mechanism. This mechanism allows system software to modify the completion timeout value. This field is applicable only to Root Ports and Endpoints that issue requests on their own behalf. This parameter must be set to NONE for the Avalon-MM with DMA interface. Completion timeouts are specified and enabled in the Device Control 2 register (0x0A8) of the PCI Express Capability Structure Version. For all other functions this field is reserved and must be hardwired to 0x0000b. Four time value ranges are defined:
Bits are set to show timeout value ranges supported. The function must implement a timeout value in the range 50 s to 50 ms. The following values specify the range:
All other values are reserved. Intel recommends that the completion timeout mechanism expire in no less than 10 ms. |
Disable completion timeout |
On/Off |
On |
Disables the completion timeout mechanism. When On, the core supports the completion timeout disable mechanism via the PCI Express Device Control Register 2. The Application Layer logic must implement the actual completion timeout mechanism for the required ranges. |