Visible to Intel only — GUID: lbl1440606584266
Ixiasoft
Visible to Intel only — GUID: lbl1440606584266
Ixiasoft
3.6. Configuration, Debug, and Extension Options
Parameter |
Value |
Description |
---|---|---|
Enable configuration via Protocol (CvP) | On/Off |
When On, the Quartus® Prime software places the Endpoint in the location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below. CvP is supported for Cyclone® 10 GX devices from the Quartus® Prime release 17.1.1 onwards. |
Enable dynamic reconfiguration of PCIe read-only registers | On/Off |
When On, you can use the Hard IP reconfiguration bus to dynamically reconfigure Hard IP read‑only registers. For more information refer to Hard IP Reconfiguration Interface. |
Enable transceiver dynamic reconfiguration | On/Off | When on, creates an Avalon-MM slave interface that software can drive to update transceiver registers. |
Enable Altera Debug Master Endpoint (ADME) | On/Off |
When On, an embedded Altera Debug Master Endpoint connects internally to the Avalon-MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It uses JTAG via the System Console to run tests and debug functions. |
Enable Arria® 10 FPGA Development Kit connection | On/Off | When On, add control and status conduit interface to the top level variant, to be connected a PCIe Development Kit component. |