Visible to Intel only — GUID: lbl1452617680916
Ixiasoft
Visible to Intel only — GUID: lbl1452617680916
Ixiasoft
1.3. Comparison of Avalon-ST, Avalon-MM and Avalon-MM with DMA Interfaces
Feature |
Avalon-ST Interface |
Avalon-MM Interface |
Avalon-MM DMA |
---|---|---|---|
IP Core License |
Free |
Free |
Free |
Native Endpoint |
Supported |
Supported |
Supported |
Root port |
Supported |
Supported |
Not supported |
Gen1 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, ×8 |
x8 |
Gen2 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, ×8 |
×4, ×8 |
Gen3 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, x8 4 |
×2, ×4, ×8 5 |
64-bit Application Layer interface |
Supported |
Supported |
Not supported |
128-bit Application Layer interface |
Supported |
Supported |
Supported |
256‑bit Application Layer interface |
Supported |
Supported |
Supported |
Maximum payload size |
128, 256, 512, 1024, 2048 bytes |
128, 256 bytes |
128, 256 bytes |
Number of tags supported for non-posted requests |
32, 64, 128, or 256 |
8 for the 64-bit interface 16 for the 128-bit interface |
16 or 256 |
Automatically handle out-of-order completions (transparent to the Application Layer) |
Not supported |
Supported |
Not Supported |
Automatically handle requests that cross 4 KB address boundary (transparent to the Application Layer) |
Not supported |
Supported |
Supported |
Polarity Inversion of PIPE interface signals |
Supported |
Supported |
Supported |
Number of MSI requests |
1, 2, 4, 8, 16, or 32 |
1, 2, 4, 8, 16, or 32 |
1, 2, 4, 8, 16, or 32 |
MSI-X |
Supported |
Supported |
Supported |
Legacy interrupts |
Supported |
Supported |
Supported |
Expansion ROM |
Supported |
Not supported |
Not supported |
PCIe bifurcation | Not supported | Not supported | Not supported |
TLP (Transmit Support) |
Avalon-ST Interface |
Avalon-MM Interface |
Avalon-MM DMA |
---|---|---|---|
Memory Read Request (Mrd) | EP/RP | EP/RP | EP/RP (Read DMA Avalon-MM Master) |
Memory Read Lock Request (MRdLk) | EP/RP | Not supported | Not supported |
Memory Write Request (MWr) | EP/RP | EP/RP | EP/RP (Write DMA Avalon-MM Master) (TX Slave - optional) |
I/O Read Request (IORd) | EP/RP | EP/RP | Not supported |
I/O Write Request (IOWr) | EP/RP | EP/RP | Not supported |
Config Type 0 Read Request (CfgRd0) | RP | RP | Not supported |
Config Type 0 Write Request (CfgWr0) | RP | RP | Not supported |
Config Type 1 Read Request (CfgRd1) | RP | RP | Not supported |
Config Type 1 Write Request (CfgWr1) | RP | RP | Not supported |
Message Request (Msg) | EP/RP | Not supported | Not supported |
Message Request with Data (MsgD) | EP/RP | Not supported | Not supported |
Completion (Cpl) | EP/RP | EP/RP | EP/RP (Read & Write DMA Avalon-MM Masters) |
Completion with Data (CplD) | EP/RP | Not supported | EP/RP (Read & Write DMA Avalon-MM Masters) |
Completion-Locked (CplLk) | EP/RP | Not supported | Not supported |
Completion Lock with Data (CplDLk) | EP/RP | Not supported | Not supported |
Fetch and Add AtomicOp Request (FetchAdd) | EP | Not supported | Not supported |
The Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.