Arria® 10 or Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 9/10/2024
Public
Document Table of Contents

1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe* Datasheet

Arria® 10 and Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with the PCI Express Base Specification 3.0 and PCI Express Base Specification 2.0 respectively.

The Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express with the Avalon® Memory-Mapped (Avalon-MM) DMA interface removes some of the complexities associated with the PCIe protocol. For example, the IP core handles TLP encoding and decoding. In addition, the IP core includes Read DMA and Write DMA engines. If you have already architected your own DMA system with the Avalon-MM interface, you may want to continue to use that system. However, you may benefit from the simplicity of having the included DMA engines. This variant is available in Platform Designer for 128- and 256-bit interfaces to the Application Layer. The Avalon-MM interface and DMA engines are implemented in FPGA soft logic.

Figure 1.  Arria® 10 or Cyclone® 10 GX PCIe Variant with Avalon-MM DMA InterfaceThe following figure shows the high-level modules and connecting interfaces for this variant.
Table 1.   Arria® 10 PCI Express Maximum Theoretical Data Throughput
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 2, 4, and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga-transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which introduces only a 1.5% overhead.
Note: Maximum theoretical data throughput values are link throughput values after accounting for coding overhead. The real application throughput is reduced by several other factors. Refer to the Understanding Throughput section of AN 456 for more details.

Units are Gigabits per second (Gbps).

Link Width
×2 ×4 ×8

PCI Express Gen1 (2.5 Gbps)

Not supported Not supported

16 Gbps

PCI Express Gen2 (5.0 Gbps)

Not supported

16 Gbps

32 Gbps

PCI Express Gen3 (8.0 Gbps)

15.75 Gbps

31.51 Gbps

63Gbps

Table 2.   Cyclone® 10 GX PCI Express Maximum Theoretical Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen1and Gen2 for 4 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1 and 5.0 giga-transfers per second for Gen2. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead.

Units are Gigabits per second (Gbps).

Link Width
×2 ×4

PCI Express Gen1 (2.5 Gbps)

Not supported Not supported

PCI Express Gen2 (5.0 Gbps)

Not supported

16 Gbps