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Ixiasoft
Visible to Intel only — GUID: nik1410905284307
Ixiasoft
1.1. Arria® 10 or Cyclone® 10 GX Avalon-MM DMA Interface for PCIe* Datasheet
Arria® 10 and Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with the PCI Express Base Specification 3.0 and PCI Express Base Specification 2.0 respectively.
The Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express with the Avalon® Memory-Mapped (Avalon-MM) DMA interface removes some of the complexities associated with the PCIe protocol. For example, the IP core handles TLP encoding and decoding. In addition, the IP core includes Read DMA and Write DMA engines. If you have already architected your own DMA system with the Avalon-MM interface, you may want to continue to use that system. However, you may benefit from the simplicity of having the included DMA engines. This variant is available in Platform Designer for 128- and 256-bit interfaces to the Application Layer. The Avalon-MM interface and DMA engines are implemented in FPGA soft logic.
Link Width | |||
---|---|---|---|
×2 | ×4 | ×8 | |
PCI Express Gen1 (2.5 Gbps) |
Not supported | Not supported | 16 Gbps |
PCI Express Gen2 (5.0 Gbps) |
Not supported |
16 Gbps |
32 Gbps |
PCI Express Gen3 (8.0 Gbps) |
15.75 Gbps |
31.51 Gbps |
63Gbps |
Link Width | ||
---|---|---|
×2 | ×4 | |
PCI Express Gen1 (2.5 Gbps) |
Not supported | Not supported |
PCI Express Gen2 (5.0 Gbps) |
Not supported |
16 Gbps |