Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Intel HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.6.4. Constraining the I/O Pins x
1.6.4.1. General Purpose I/O 1.6.4.2. Dedicated Active Serial Interface
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Intel HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.7.2.2. Reference Design Application Program

Figure 6. Reference Design Application Program Flow Diagram
Flow diagram sequence description:
  1. The application program starts with identifying the flash device attached to the FPGA.
    Note: The flash devices serve as samples to demonstrate this reference design only.
  2. The application program performs sector protection and erases the protected sector:
    1. To perform sector protect, the application program:
      1. Performs write enable command.
      2. Performs write status register command to set block protect (BP) bit and Top/Bottom(TB) bit.
      3. Polls write in progress (WIP) bit ( bit 0 of status register) until it returns a 0 (ready).
      4. Performs read status register command to check if sector protect operation succeeded or failed.
    2. To perform sector erase, the application program:
      1. Performs write enable command.
      2. Performs sector erase command.
      3. Polls write in progress (WIP) bit ( bit 0 of status register) until it return a 0 (ready).
      4. Performs read status register to check whether erase operation succeeded or failed.
  3. Erase error occurred because the sector is protected. The application program clears the error bit through:
    • Clear flag status register command (EPCQ-L or Micron*).
    • Clear status register command (Cypress*).
  4. The application program disables the sector protect:
    1. Performs write enable command.
    2. Performs write status register command to clear BP bit and TB bit.
    3. Polls WIP bit ( bit 0 of status register) until it returns a 0 (ready).
    4. Performs read status register command to check whether BP bit and TB bit has succeeded clear.
  5. The application program performs flash device programming after the sector is not protected. The application program:
    1. Performs write memory into the address with empty memory.
    2. Polls WIP bit (bit 0 of status register) until it returns a 0 (ready)
    3. Performs read back memory of the address to confirm the address has programmed.
  6. Repeat Step 2 and read back memory of the address. Memory is not erased because the sector is protected.
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