Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Intel HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.6.4. Constraining the I/O Pins x
1.6.4.1. General Purpose I/O 1.6.4.2. Dedicated Active Serial Interface
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash Perform the Read Memory (Extended Mode) Perform the Dual-Output Fast Read (Dual-SPI Mode) 1.8.6. Program Flash
1.9. Intel HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.8.5. Read Memory from the Flash

The following registers are used to perform the read memory:

  • Operating protocols setting register
  • Control register
  • Read instruction register

Perform the Read Memory (Extended Mode)

proc read { } {
global mp operating_protocols_setting control_register read_instr
master_write_32 $mp $operating_protocols_setting 0x00000000
master_write_32 $mp $control_register 0x00000001
master_write_32 $mp $read_instr 0x00000003
master_read_32 $mp 0x0100000 0x1
}

To perform the read memory for the extended mode, follow these steps:

  1. Define the global variables.
  2. Write to the operating protocols setting register to set the transfer mode of the read memory operation. In this example, the transfer mode for read is (1-1-1).
    1. Set the instruction transfer mode [1:0] to 0, read address transfer mode [13:12] to 0, and read data out transfer mode [17:16] to 0.
  3. Write to the control register to choose the byte addressing mode of the read memory operation.
    1. This example is using the 3-byte addressing mode. Set bit 8 to 0.
  4. Write to the read instruction register to customize the read memory operation.
    1. Set the read operation code [7:0] to 03 as 03h is the operation code for read.
    2. Set the dummy cycles [12:8] to 0 as the read operation does not contain any dummy cycles.
  5. After setting the registers, you can perform read memory content in the address.
    1. In this example, 1 word of data is read from address 0x01000000.

Perform the Dual-Output Fast Read (Dual-SPI Mode)

proc dual_output_fast_read { } {
global mp operating_protocols_setting control_register read_instr
master_write_32 $mp $operating_protocols_setting 0x00011001
master_write_32 $mp $control_register 0x00000101
master_write_32 $mp $read_instr 0x00000A3B
master_read_32 $mp 0x00000100 0x1
}

To perform the dual-output fast read mode, follow these steps:

  1. Define the global variables.
  2. Write to the operating protocols setting register to set the transfer mode of the read memory operation. In this example, the transfer mode for read is (2-2-2).
    1. Set the instruction transfer mode [1:0] to 1, read address transfer mode [13:12] to 1, and read data out transfer mode [17:16] to 1.
  3. Write to the control register to choose the byte addressing mode of the read memory operation.
    1. This example is using the 4-byte addressing mode. Set bit 8 to 1.
  4. Write to the read instruction register to customize the read memory operation.
    1. Set the read operation code [7:0] to 3B as 3Bh is the operation code for the dual-output fast read.
    2. Set the dummy cycles [12:8] to A as the dual-output fast read operation contains 10 dummy cycles.
  5. After setting the registers, you can perform dual-output fast read memory content in the address.
    1. In this example, the memory content is read from address 0x00000100.
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