Stratix V Avalon-MM Interface for PCIe Solutions: User Guide

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ID 683411
Date 5/21/2017
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Design Example 3. Parameter Settings 4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 5. Registers 6. Interrupts for Endpoints 7. Error Handling A. PCI Express Protocol Stack 8. Transceiver PHY IP Reconfiguration 9. Throughput Optimization 10. Design Implementation 11. Additional Features 12. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Stratix V Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Design Example x
2.1. Running Qsys 2.2. Generating the Example Design 2.3. Understanding Simulation Log File Generation 2.4. Running a Gate-Level Simulation 2.5. Simulating the Single DWord Design 2.6. Generating Synthesis Files 2.7. Creating a Quartus® Prime Project 2.8. Compiling the Design 2.9. Programming a Device 2.10. Understanding Channel Placement Guidelines
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. Avalon Memory‑Mapped System Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals 4.4. Clock Signals 4.5. Reset 4.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.7. Hard IP Status Signals 4.8. Physical Layer Interface Signals
4.7. Hard IP Status Signals x
4.7.1. Hard IP Reconfiguration Interface
4.8. Physical Layer Interface Signals x
4.8.1. Hard IP Status Extension 4.8.2. Serial Data Signals 4.8.3. PIPE Interface Signals 4.8.4. Test Signals
4.8.2. Serial Data Signals x
4.8.2.1. Physical Layout of Hard IP in Stratix V GX/GT/GS Devices 4.8.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Interrupts for Endpoints x
6.1. Enabling MSI or Legacy Interrupts 6.2. Generation of Avalon-MM Interrupts 6.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
9. Throughput Optimization x
9.1. Throughput of Posted Writes 9.2. Throughput of Non-Posted Reads
10. Design Implementation x
10.1. Making Analog QSF Assignments Using the Assignment Editor 10.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 10.3. Recommended Reset Sequence to Avoid Link Training Issues 10.4. SDC Timing Constraints
11. Additional Features x
11.1. Configuration over Protocol (CvP) 11.2. Autonomous Mode 11.3. ECRC
11.2. Autonomous Mode x
11.2.1. Enabling Autonomous Mode 11.2.2. Enabling CvP Initialization
11.3. ECRC x
11.3.1. ECRC on the RX Path 11.3.2. ECRC on the TX Path
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
12.2. Link Training x
12.2.1. Debugging Link that Fails To Reach L0
D. Document Revision History x
D.1. Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Design Example
3. Parameter Settings
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
5. Registers
6. Interrupts for Endpoints
7. Error Handling
A. PCI Express Protocol Stack
8. Transceiver PHY IP Reconfiguration
9. Throughput Optimization
10. Design Implementation
11. Additional Features
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

2.2. Generating the Example Design

  1. On the Generate menu, select Generate Testbench System. The Generation dialog box appears.
  2. Under Testbench System, set the following options:
    1. For Create testbench Qsys system, select Standard, BFMs for standard Qsys interfaces.
    2. For Create testbench simulation model, select Verilog.
  3. You can retain the default values for all other parameters.
  4. Click Generate.
  5. After Qsys reports Generation Completed, click Close.
  6. On the File menu, click Save.

The following table lists the testbench and simulation directories Qsys generates.

Table 8.  Qsys System Generated Directories

Directory

Location

Qsys system

<project_dir>/ep_g2x4

Testbench

<project_dir>/ep_g2x4/testbench/<cad_vendor>

Simulation Model

<project_dir>/ep_g2x4/testbench/ep_g2x4_tb/simulation/

The design example simulation includes the following components and software:

  • The Qsys system
  • A testbench. You can view this testbench in Qsys by opening <project_dir>/ep_g2x4/testbench/ep_g2x4_tb.qsys.
  • The ModelSim software
Note: You can also use any other supported third-party simulator to simulate your design.

Complete the following steps to run the Qsys testbench:

  1. In a terminal window, change to the <project_dir>/ep_g2x4/testbench/mentor directory.
  2. Start the ModelSim® simulator.
  3. Type the following commands in a terminal window:
    1. do msim_setup.tcl
    2. ld_debug
    3. run 140000 ns

The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window:

  1. Various configuration accesses to the Avalon‑MM Stratix V Hard IP for PCI Express in your system after the link is initialized
  2. Setup of the Address Translation Table for requests that are coming from the DMA component
  3. Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared memory
  4. Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared memory
  5. Data comparison and report of any mismatch

The following example shows the transcript from a successful simulation run.

Transcript from ModelSim Simulation of Gen2 x4 Endpoint 


# 464 ns Completed initial configuration of Root Port. 
# INFO: 2657 ns EP LTSSM State: DETECT.ACTIVE 
# INFO: 3661 ns RP LTSSM State: DETECT.ACTIVE 				
# INFO: 6049 ns EP LTSSM State: POLLING.ACTIVE 
# INFO: 6909 ns RP LTSSM State: POLLING.ACTIVE 
# INFO: 9037 ns RP LTSSM State: POLLING.CONFIG 
# INFO: 9441 ns EP LTSSM State: POLLING.CONFIG 
# INFO: 10657 ns EP LTSSM State:CONFIG.LINKWIDTH.START 
# INFO: 10829 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 11713 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT 
# INFO: 12253 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT 
# INFO: 12573 ns RP LTSSM State: CONFIG.LANENUM.WAIT 
# INFO: 13505 ns EP LTSSM State: CONFIG.LANENUM.WAIT 
# INFO: 13825 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT 
# INFO: 13853 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT 
# INFO: 14173 ns RP LTSSM State: CONFIG.COMPLETE 
# INFO: 14721 ns EP LTSSM State: CONFIG.COMPLETE 
# INFO: 16001 ns EP LTSSM State: CONFIG.IDLE 
# INFO: 16093 ns RP LTSSM State: CONFIG.IDLE 
# INFO: 16285 ns RP LTSSM State: L0 
# INFO: 16545 ns EP LTSSM State: L0 
# INFO: 19112 ns Configuring Bus 001, Device 001, Function 00
# INFO: 19112 ns EP Read Only Configuration Registers: 
# INFO: 19112 ns Vendor ID: 0000 
# INFO: 19112 ns Device ID: 0001 
# INFO: 19112 ns Revision ID: 01 
# INFO: 19112 ns Class Code: 000000 
# INFO: 19112 ns Subsystem Vendor ID: 0000 
# INFO: 19112 ns Subsystem ID: 0000 
# INFO: 19112 ns Interrupt Pin: INTA used
# INFO: 20584 ns PCI MSI Capability Register: 
# INFO: 20584 ns 64-Bit Address Capable: Supported 
# INFO: 20584 ns Messages Requested: 4 
# INFO: 28136 ns EP PCI Express Link Status Register (1041): 
# INFO: 28136 ns Negotiated Link Width: x4 
# INFO: 28136 ns Slot Clock Config: System Reference Clock Used 
# INFO: 29685 ns RP LTSSM State: RECOVERY.RCVRLOCK 
# INFO: 30561 ns EP LTSSM State: RECOVERY.RCVRLOCK 
# INFO: 31297 ns EP LTSSM State: RECOVERY.RCVRCFG 
# INFO: 31381 ns RP LTSSM State: RECOVERY.RCVRCFG 
# INFO: 32661 ns RP LTSSM State: RECOVERY.IDLE 
# INFO: 32961 ns EP LTSSM State: RECOVERY.IDLE 
# INFO: 33153 ns EP LTSSM State: L0 
# INFO: 33237 ns RP LTSSM State: L0 
# INFO: 34696 ns Current Link Speed: 2.5GT/s INFO: 34696 ns 
# INFO: 36168 ns EP PCI Express Link Control Register (0040): 
# INFO: 36168 ns Common Clock Config: System Reference Clock Used 
# INFO: 37960 ns EP PCI Express Capabilities Register (0002): 
# INFO: 37960 ns Capability Version: 2  
# INFO: 37960 ns Port Type: Native Endpoint  
# INFO: 37960 ns EP PCI Express Device Capabilities Register(00008020):
# INFO: 37960 ns Max Payload Supported: 128 Bytes  
# INFO: 37960 ns Extended Tag: Supported 
# INFO: 37960 ns Acceptable L0s Latency: Less Than 64 ns 
# INFO: 37960 ns Acceptable L1 Latency: Less Than 1 us 
# INFO: 37960 ns Attention Button: Not Present 
# INFO: 37960 ns Attention Indicator: Not Present 
# INFO: 37960 ns Power Indicator: Not Present 
# INFO: 37960 ns EP PCI Express Link Capabilities Register (01406041):
# INFO: 37960 ns Maximum Link Width: x4 
# INFO: 37960 ns Supported Link Speed: 2.5GT/s 
# INFO: 37960 ns L0s Entry: Not Supported 
# INFO: 37960 ns L1 Entry: Not Supported 
# INFO: 37960 ns L0s Exit Latency: 2 us to 4 us 
# INFO: 37960 ns L1 Exit Latency: Less Than 1 us 
# INFO: 37960 ns Port Number: 01 
# INFO: 37960 ns Surprise Dwn Err Report: Not Supported
# INFO: 37960 ns DLL Link Active Report: Not Supported 
# INFO: 37960 ns EP PCI Express Device Capabilities 2 Register (0000001F):
# INFO: 37960 ns Completion Timeout Rnge: ABCD (50us to 64s) 
# INFO: 39512 ns EP PCI Express Device Control Register (0110): 
# INFO: 39512 ns Error Reporting Enables: 0 
# INFO: 39512 ns Relaxed Ordering: Enabled 
# INFO: 39512 ns Error Reporting Enables: 0 
# INFO: 39512 ns Relaxed Ordering: Enabled 
# INFO: 39512 ns Max Payload: 128 Bytes 
# INFO: 39512 ns Extended Tag: Enabled 
# INFO: 39512 ns Max Read Request: 128 Bytes 
# INFO: 39512 ns EP PCI Express Device Status Register (0000): 
# INFO: 41016 ns EP PCI Express Virtual Channel Capability: 
# INFO: 41016 ns Virtual Channel: 1 
# INFO: 41016 ns Low Priority VC: 0 
# INFO: 46456 ns BAR Address Assignments: 
# INFO: 46456 ns BAR Size Assigned Address Type 
# INFO: 46456 ns BAR1:0 4 MBytes 00000001 00000000 Prefetchable 
# INFO: 46456 ns BAR2 32 KBytes 00200000 Non-Prefetchable 
# INFO: 46456 ns BAR3 Disabled 
# INFO: 46456 ns BAR4 Disabled 
# INFO: 46456 ns BAR5 Disabled 
# INFO: 46456 ns ExpROM Disabled 
# INFO: 48408 ns Completed configuration of Endpoint BAR 
# INFO: 50008 ns Starting Target Write/Read Test. 
# INFO: 50008 ns Target BAR = 0 
# INFO: 50008 ns Length = 000512, Start Offset = 000000 
# INFO: 54368 ns Target Write and Read compared okay! 
# INFO: 54368 ns Starting DMA Read/Write Test. 
# INFO: 54368 ns Setup BAR = 2 
# INFO: 54368 ns Length = 000512, Start Offset = 000000 
# INFO: 60609 ns Interrupt Monitor: Interrupt INTA Asserted 
# INFO: 60609 ns Clear Interrupt INTA 
# INFO: 62225 ns Interrupt Monitor: Interrupt INTA Deasserted 
# INFO: 69361 ns MSI recieved! 
# INFO: 69361ns DMA Read and Write compared okay! 
# SUCCESS: Simulation stopped due to	successful completion! # Break at .ep_g1x4_tb/simulation/submodules//altpcietb_bfm_log.v line 78
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