Visible to Intel only — GUID: nik1410905284925
Ixiasoft
Visible to Intel only — GUID: nik1410905284925
Ixiasoft
1.2. Features
- Rearchitected SR-IOV bridge to provide more 2056 virtual functions.
- Automatic generation of basic SignalTap® Logic Analyzer files to facilitate debugging.
- Simulation support for Gen3 PIPE mode using the ModelSim, NCSIM, and VCS simulators.
- Support for OpenCore Plus IP evaluation in the Quartus® Prime Pro Edition software.
The Stratix V Hard IP for PCI Express with the Avalon-MM interface supports the following features:
- Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
- Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Root Ports and Endpoints.
- Dedicated 16 kilobyte (KB) receive buffer.
- Optional hard reset controller for Gen2.
- Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.
- Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.
- Qsys example designs demonstrating parameterization, design modules, and connectivity.
- Extended credit allocation settings to better optimize the RX buffer space based on application type.
- Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.
- Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions.
- Support for Gen3 PIPE simulation.
- Easy to use:
- Flexible configuration.
- No license requirement.
- Example designs to get started.
Feature |
Avalon-ST Interface |
Avalon-MM Interface |
Avalon-MM DMA |
---|---|---|---|
IP Core License |
Free |
Free |
Free |
Native Endpoint |
Supported |
Supported |
Supported |
Legacy Endpoint 1 |
Supported |
Not Supported |
Not Supported |
Root port |
Supported |
Supported |
Not Supported |
Gen1 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, ×8 |
Not Supported |
Gen2 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4, ×8 |
×4, ×8 |
Gen3 |
×1, ×2, ×4, ×8 |
×1, ×2, ×4 |
×4, ×8 |
64-bit Application Layer interface |
Supported |
Supported |
Not supported |
128-bit Application Layer interface |
Supported |
Supported |
Supported |
256‑bit Application Layer interface |
Supported |
Not Supported |
Supported |
Maximum payload size |
128, 256, 512, 1024, 2048 bytes |
128, 256 bytes |
128, 256 bytes |
Number of tags supported for non-posted requests |
256 |
8 for the 64-bit interface 16 for the 128-bit interface |
16 |
62.5 MHz clock |
Supported |
Supported |
Not Supported |
Automatically handle out-of-order completions (transparent to the Application Layer) |
Not supported |
Supported |
Supported |
Automatically handle requests that cross 4 KB address boundary (transparent to the Application Layer) |
Not supported |
Supported |
Supported |
Polarity Inversion of PIPE interface signals |
Supported |
Supported |
Supported |
ECRC forwarding on RX and TX |
Supported |
Not supported |
Not supported |
Number of MSI requests |
1, 2, 4, 8, 16, or 32 |
1, 2, 4, 8, 16, or 32 |
1, 2, 4, 8, 16, or 32 |
MSI-X |
Supported |
Supported |
Supported |
Legacy interrupts |
Supported |
Supported |
Supported |
Expansion ROM |
Supported |
Not supported |
Not supported |
PCIe bifurcation | Not supported | Not supported | Not supported |
Transaction Layer Packet type (TLP) (transmit support) |
Avalon-ST Interface |
Avalon-MM Interface |
Avalon-MM DMA |
---|---|---|---|
Memory Read Request (Mrd) | EP/RP | EP/RP | EP |
Memory Read Lock Request (MRdLk) | EP/RP | EP | |
Memory Write Request (MWr) | EP/RP | EP/RP | EP |
I/O Read Request (IORd) | EP/RP | EP/RP | |
I/O Write Request (IOWr) | EP/RP | EP/RP | |
Config Type 0 Read Request (CfgRd0) | RP | RP | |
Config Type 0 Write Request (CfgWr0) | RP | RP | |
Config Type 1 Read Request (CfgRd1) | RP | RP | |
Config Type 1 Write Request (CfgWr1) | RP | RP | |
Message Request (Msg) | EP/RP | EP/RP | |
Message Request with Data (MsgD) | EP/RP | EP/RP | |
Completion (Cpl) | EP/RP | EP/RP | EP |
Completion with Data (CplD) | EP/RP | EP/RP | EP |
Completion-Locked (CplLk) | EP/RP | ||
Completion Lock with Data (CplDLk) | EP/RP | ||
Fetch and Add AtomicOp Request (FetchAdd) | EP |
The Stratix V Avalon-MM Interface for PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.