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Ixiasoft
4.3.2.1. Receive Path Blocks
- RX PMA
- RX PCS
- RX MAC
- RX Regroup Block
- n = Number of calender pages
- m = Number of lanes
- n = Number of calender pages
- m = Number of lanes
- RX PMA
- RX PCS
- RX MAC
- RX Regroup Block
RX PMA
The Interlaken IP core RX PMA deserializes data that the IP core receives on the serial lines of the Interlaken link. RX PMA contains RS FEC block in PAM4 mode of E-tile devices and three RS FEC (544,514) blocks in 6x 53.125 Gbps PAM4 mode configuration. Each RS FEC block serves four FEC channels in the aggregate mode.
RX PCS
- Detects word lock and word synchronization.
- Checks running disparity.
- Reverses gear-boxing and 64/67B encoding.
- Descrambles the data.
- Delineates meta frame boundaries.
- Performs CRC32 checking.
- Sends lane status information to the calendar and status blocks, if Include in-band flow control functionality is turned on.
- Performs asynchronous operations and receiver alignment using RX Align FIFO.
- Performs the Interlaken inverse transcoding function on the data received from the RX RS FEC (544, 514) in E-tile PAM4 mode device variations.
For more information about error conditions, refer to the ILKN_FEC_XCODER_TX_ILLEGAL_STATE (offset 0x80) and ILKN_FEC_XCODER_RX_UNCOR_FECCW (offset 0x81) registers. You can also obtain more details from the FEC status, FEC correctable and uncorrectable registers documented in the RS-FEC Registers section of the E-Tile Transceiver PHY User Guide.
RX MAC
- Data de-striping, including lane alignment and burst assembly from the PCS lanes.
- CRC24 validation.
- Calendar recovery, if Include in-band flow control functionality is turned on.
RX Regroup Block
The Interlaken IP core RX regroup block translates the IP core internal data format to the outgoing user application data irx_dout_words format.
For details on transceiver initialization, please refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide or the E-Tile Transceiver PHY User Guide.