4.9. Out-of-Band Flow Control
This figure lists the signals on the four interfaces of the out-of-band flow control block.
The out-of-band flow control block is provided as two separate modules that can be stitched to the Interlaken IP core and user logic. You can optionally instantiate these blocks in your own custom logic. To enable the use of these out-of-band modules, the signals on the far left side of the figure must be connected to user logic, and the signals on the far right side of the figure should be connected to the complementary flow control blocks of the Interlaken link partner.
Clock Name | Interface | Direction | Recommended Frequency (MHz) | Description |
---|---|---|---|---|
rx.fc_clk | RX Out-of-band | Input | 100 | Clocks the incoming out‑of‑band flow control interface signals described in the Interlaken specification. This clock is received from an upstream TX out‑of‑band flow control block associated with the Interlaken link partner. The recommended frequency for the RX fc_clk clock is 100 MHz, which is the maximum frequency allowed by the Interlaken specification. |
tx.fc_clk | TX Out-of-band | Output | 100 | Clocks the outgoing out‑of‑band flow control interface signals described in the Interlaken specification. This clock is generated by the out‑of‑band flow control block and sent to a downstream RX out‑of‑band flow control block associated with the Interlaken link partner. The frequency of this clock must be half the frequency of the double_fc_clk clock. The recommended frequency for the TX fc_clk clock is 100 MHz, which is the maximum frequency allowed by the Interlaken specification. |
sys_clk | RX Application | Input | 200 | Clocks the outgoing calendar and status information on the application side of the block. The frequency of this clock must be at least double the frequency of the RX input clock fc_clk. Therefore, the recommended frequency for the sys_clk clock is 200 MHz. |
double_fc_clk | TX Application | Input | 200 | Clocks the incoming calendar and status information on the application side of the block. The frequency of this clock must be double the frequency of the TX output clock fc_clk. Therefore, the recommended frequency for the double_fc_clk clock is 200 MHz. |
Signal Name |
Direction |
Width (Bits) |
Description |
---|---|---|---|
tx.fc_clk |
Output |
1 |
Output reference clock to a downstream out-of-band RX block. Clocks the fc_data and fc_sync signals. You must connect this signal to a device pin. |
tx.fc_data |
Output |
1 |
Output serial data pin to a downstream out-of-band RX block. You must connect this signal to a device pin. |
tx.fc_sync |
Output |
1 |
Output sync control pin to a downstream out-of-band RX block. You must connect this signal to a device pin. |
Signal Name |
Direction |
Width (Bits) |
Description |
---|---|---|---|
double_fc_clk |
Input |
1 |
Reference clock for generating the flow control output clock fc_clk. The frequency of the double_fc_clk clock must be double the intended frequency of the TX fc_clk output clock. |
double_fc_arst |
Input |
1 |
Asynchronous reset for the out-of-band TX block. |
ena_status |
Input |
1 |
Enable transmission of the lane status and link status to the downstream out-of-band RX block. If this signal is asserted, the lane and link status information is transmitted on fc_data. If this signal is not asserted, only the calendar information is transmitted on fc_data. |
lane_status |
Input |
Number of Lanes |
Lane status to be transmitted to a downstream out-of-band RX block if ena_status is asserted. Width is the number of lanes. |
link_status |
Input |
1 |
Link status to be transmitted to a downstream out-of-band RX block if ena_status is asserted. |
calendar |
Input |
16 |
Calendar status to be transmitted to a downstream out-of-band RX block. |
Signal Name |
Direction |
Width (Bits) |
Description |
---|---|---|---|
rx.fc_clk |
Input |
1 |
Input reference clock from an upstream out-of-band TX block. This signal clocks the fc_data and fc_sync signals. You must connect this signal to a device pin. |
rx.fc_data |
Input |
1 |
Input serial data pin from an upstream out-of-band TX block. You must connect this signal to a device pin. |
rx.fc_sync |
Input |
1 |
Input sync control pin from an upstream out-of-band TX block. You must connect this signal to a device pin. |
Signal Name |
Direction |
Width (Bits) |
Description |
---|---|---|---|
sys_clk |
Input |
1 |
Reference clock for capturing RX calendar, lane status, and link status. Frequency must be at least double the frequency of the TX fc_clk input clock. |
sys_arst |
Input |
1 |
Asynchronous reset for the out-of-band RX block. |
status_update |
Output |
1 |
Indicates a new value without CRC4 errors is present on at least one of lane_status or link_status in the current sys_clk cycle. The value is ready to be read by the application logic. |
lane_status |
Output |
Number of Lanes |
Lane status bits received from an upstream out-of-band TX block on fc_data. Width is the number of lanes. |
link_status |
Output |
1 |
Link status bit received from an upstream out-of-band TX block on fc_data. |
status_error |
Output |
1 |
Indicates corrupt lane or link status. A new value is present on at least one of lane_status or link_status in the current sys_clk cycle, but the value has at least one CRC4 error. |
calendar |
Output |
16 |
Calendar bits received from an upstream out-of-band TX block on fc_data. |
calendar_update |
Output |
1 |
Indicates a new value without CRC4 errors is present on calendar in the current sys_clk cycle. The value is ready to be read by the application logic. |
calendar_error |
Output |
1 |
Indicates corrupt calendar bits. A new value is present calendar in the current sys_clk cycle, but the value has at least one CRC4 error. |