Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

4.5.4.1. Multi-Segment Interface Example

The following example illustrates how to use the Interlaken IP core TX and RX multi-segment interface:

TX Multi-Segment

This example illustrates the expected behavior of multi-segment mode Interlaken IP core at the TX user interface during a 65 byte packet transfer in four-segment interleave mode.
Figure 28. TX Multi-Segment User Interface Example

Even though there are 4-bit allocated to the sob and sop bus, only a maximum of two segment chunks are supported in any given cycle. Because of this reason, you need only two-bit eob, two sets of eopbits and channel numbers.

In this example, in cycle 0, the second segment starts at segment 0 while the first segment data occupies segment 3, 2, and 1. In cycle 1, the first segment of data occupies segment 3 and 2 while the second segment of data occupies the segment 0 and 1.

There are two burst starting in cycle 0. In sob= 4'b1001, the sob[3] refers to the start of a burst at word 15. The sob[0] refers to another start of a burst at word 3. The packet ends in cycle 0. Hence, eopbits=4'b1000 indicates the last word containing eight bytes. eob=1'b1 is for the first segment chunk. The eopbits1 indicates no end of packet since eopbits1[3]=0. The two channel numbers are h'AB and h'CD, respectively.

There is one burst ends and one burst starts in cycle 1. In sob= 4'b0010, the burst in the first segment continues the second segment of the last cycle. There is no sob[3] set in this cycle. The sob[1]=1 of the second segment refers to the start of a burst at word 7. The packet (first segment chunk) ends in this cycle, hence eopbits=4'b1010 indicating the last word contains two bytes. The eob=1'b1 is for the first segment chunk. The eopbits1 indicates no EOP since eopbits1[3]=0. Only the channel number for the second segment chunk is valid, which is 'h02. This channel number corresponds to the burst indicated by sob[1]=1'b1. A channel number is always associated to a start of a burst.

There is one burst ends and one burst starts in cycle 2. In sob= 4'b0100, the burst in the first segment continues the second segment of the last cycle. There is no sob[3] set in this cycle. The packet ends in this cycle, hence, eopbits=4'h1000, indicates the last word containing eight bytes. The eob=1'b1 is for the first segment chunk. The sob[2]=1 of the second segment chunk refers to the start of burst at word 11. The packet ends in this cycle, hence eopbits1=4'b1011 indicates the last word containing three bytes. Also, eob1=1'b1 is the EOB for the second segment chunk. Only the channel number for the second segment chunk is valid here, which is 'h34. This channel number corresponds to the burst indicated by sob[2]=1'b1.

RX Multi-Segment

Below example illustrates behavior of multi-segment mode of the Interlaken IP core at the RX user interface.
Figure 29. RX Multi-Segment User Interface Example
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