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Ixiasoft
5.4. Management Interface Signals
The management interface signals are available for the Avalon® -MM (AVMM) interface.
Signal Name | Feature Support | Width (Bits) | I/O Direction | Description |
---|---|---|---|---|
mm_clk | ILK and ILA | 1 | Input | Management clock. Clocks the register accesses. It is also used for clock rate monitoring and some analog calibration procedures. You must run this clock at a frequency in the range of 100 MHz–125 MHz. |
mm_read | 1 | Input | Read access to the register ports. |
|
mm_write | 1 | Input | Write access to the register ports. |
|
mm_addr | 16 | Input | Address to access the register ports. |
|
mm_rdata | 32 | Output | When mm_rdata_valid is high, mm_rdata holds valid read data. |
|
mm_rdata_valid | 1 | Output | Valid signal for mm_rdata. |
|
mm_wdata | 32 | Input | When mm_write is high, mm_wdata holds valid write data. |
|
mm_waitrequest | 1 | Output | Busy signal for mm_rdata. |