5.6. Interlaken Link and Miscellaneous Signals
Signal Name | Feature Support | Width (Bits) | I/O Direction | Description |
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rx_pin | ILK and ILA | Number of lanes | Input | Each bit represents the differential pair on an RX Interlaken lane. |
tx_pin | Number of lanes | Output | Each bit represents the differential pair on a TX Interlaken lane. | |
rx_pin_n | Number of lanes | Input | For the PAM4 loopback example design, rx_pin_n receives data from tx_pin_n. | |
tx_pin_n | Number of lanes | Output | For the PAM4 loopback example design, tx_pin_n drives data to rx_pin_n. |
Signal Name 15 | Feature Support | Width (Bits) | I/O Direction | Description |
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tx_lanes_aligned | ILK and ILA | 1 | Output | Indicates whether all of the transmitter lanes are aligned and are ready to send traffic. |
itx_overflow | ILK only | 1 | Output | An error flag indicating that the Transmit buffer is currently overflowing. This signal is asserted for the duration of the overflow condition. It is asserted in the first clock cycle in which the overflow occurs, and remains asserted until the Transmit buffer pointers indicate that no overflow condition exists. |
itx_underflow | ILK only | 1 | Output | An error flag indicating that the Transmit buffer is currently underflowed. In normal operation, this signal may be asserted temporarily immediately after the Interlaken IP core comes out of reset. |
Signal Name 16 | Feature Support | Width (Bits) | I/O Direction | Description |
---|---|---|---|---|
rx_lanes_aligned | ILK and ILA | 1 | Output | Indicates whether all of the receiver lanes are aligned and are ready to receive traffic. |
sync_locked | ILK and ILA | Number of lanes | Output | Receive lane has locked on the remote transmitter meta Frame. These signals are level signals: all bits are expected to stay high unless a problem occurs on the serial line. |
word_locked | ILK and ILA | Number of lanes | Output | Receive lane has identified the 67-bit word boundaries in the serial stream. These signals are level signals: all bits are expected to stay high unless a problem occurs on the serial line. |
crc24_err | ILK and ILA | 1 | Output | A CRC24 error flag covering both control word and data word. You can use this signal to count the number of CRC24 errors. This signal is asserted as a single cycle wide pulse in E-tile IP core variations and as a multi-cycle wide pulse in L-tile/H-tile IP core variations. |
crc32_err | ILK and ILA | Number of lanes | Output | An error flag indicating diagnostic CRC32 failures per lane. This signal is asserted as a single cycle wide pulse in E-tile IP core variations and as a multi-cycle wide pulse in L-tile/H-tile IP core variations. |
irx_overflow | ILK only | 0 | Output | This signal is tied to 0 and it is not used. |
rdc_overflow | ILK only | 0 | Output | This signal is tied to 0 and it is not used. |
rg_overflow | ILK only | 1 | Output | An error flag indicating that the Reassembly FIFO is currently overflowed. The Reassembly FIFO is the receiver FIFO that feeds directly to the user data interface. |
rxfifo_fill_ level | ILK only | RXFIFO_ADDR_ WIDTH | Output | The fill level of the Reassembly FIFO, in units of 64-bit words. The width of this signal is the value of the RXFIFO_ADDR_WIDTH parameter, which is 12 by default. You can use this signal to monitor when the RX Reassembly FIFO is empty. |
sop_cntr_inc | ILK only | 1 | Output | A pulse indicating that the IP core receiver user data interface received a start-of- packet (SOP). You can use this signal to increment a count of SOPs the application observes on the receive interface. |
eop_cntr_inc | ILK only | 1 | Output | A pulse indicating that the IP core receiver user data interface received an end-of-packet (EOP). You can use this signal to increment a count of EOPs the application observes on the receive interface. |
sop_cntr_inc1 | ILK only | Output | A pulse indicating that the IP core receiver user data interface received a start-of- packet (SOP) on second segment chunk. You can use this signal to increment a count of SOPs the application observes on the receive interface. This signal is only available in muti-segment mode of IP core variations. |
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eop_cntr_inc1 | ILK only | Output | A pulse indicating that the IP core receiver user data interface received an end-of-packet (EOP) on second segment chunk. You can use this signal to increment a count of EOPs the application observes on the receive interface. This signal is only available in muti-segment mode of IP core variations. |
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nad_cntr_inc | ILK only | 0 | Output | This signal is tied to 0 and it is not used. |
rx_xcoder_uncor_feccw | ILK and ILA | [XCODER_LANES-1:0]] | Output | Indicates uncorrectable FEC code word. This signal is also accessible through status register and may not align with the irx_data signal. This signal is only available in PAM4 mode of E-tile device variations. |
Signal Name | Width (Bits) | I/O Direction | Description |
---|---|---|---|
burst_max_in | 4 | Input | Encodes the BurstMax parameter for the IP core. The actual value of the BurstMax parameter must be a multiple of 64 bytes. While traffic is present, this input signal should remain static. However, when no traffic is present, you can modify the value of the burst_ max_in signal to modify the BurstMax value of the IP core. The IP core supports the following valid values for this signal:
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burst_short_in | 4 | Input | Encodes the BurstShort parameter for the IP core. The IP core supports the following valid value for this parameter:
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burst_min_in | 4 | Input | Encodes the BurstMin parameter for the IP core. The IP core supports the following valid values for this signal:
Intel® recommends that you modify the value of this input signal only when no traffic is present on the TX user data interface. You do not need to reset the IP core. |
Signal Name | Feature Support | Width (Bits) | I/O Direction | Description |
---|---|---|---|---|
itx_eccstatus | ILK only | 2 | Output | Indicates the TX ECC status.
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irx_eccstatus | ILK only | 2 | Output | Indicates the RX ECC status.
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15 Synchronous with tx_usr_clk.
16 Synchronous with rx_usr_clk.
17 This value is not supported for number of words=4.
18 This value is not supported for number of words= 8 and number of words= 16 .