Interlaken (2nd Generation) Intel® FPGA IP User Guide

ID 683396
Date 12/04/2023
Public
Document Table of Contents

1.1. Features

The Interlaken (2nd Generation) Intel FPGA IP has the following features:
  • General features:
    • Compliant with the Interlaken Protocol Specification, Revision 1.2.
    • Supports 4, 6, 8, 10, and 12 serial lanes in configurations that provide up to 318.75 Gbps raw bandwidth.
    • Supports per-lane data rates of 6.25, 10.3125, 12.5, 25.28, 25.78, 25.78125, and 53.125 Gbps using Intel FPGA on-chip high-speed transceivers.
  • User interface features:
    • Supports dynamically configurable BurstMax and BurstMin values.
    • Supports Packet mode and Interleaved mode for user data transfer.
    • Supports up to 256 logical channels in out-of-the-box configuration.
    • Supports multi-segment user interface.
  • Flow-control features:
    • Supports optional out-of-band flow control blocks.
    • Supports optional user-controlled in-band flow control with 1, 2, 4, 8, or 16 16-bit calendar pages.
    • Supports error correction code (ECC) for memory block implementation with the IP.
  • Line-side features:
    • Supports per-lane data rate of 53.125 Gbps using pulse amplitude modulation (PAM4) mode in E-tile variations.
    • Supports per lane data rates of 6.25, 10.3125, 12.5, 25.28, 25.78, and 25.78125 Gbps using non-return-to-zero (NRZ) mode in E-tile variations.
  • PHY features:
    • Supports PMA adaptation.
  • Interlaken Look-aside mode:
    • Supports per lane data rates of 6.25, 10.3125, 12.5, 25.28, 25.78 and 25.78125 Gbps using NRZ and 53.125 Gbps using PAM4 mode in E-tile variations.
    • Supports packet mode for user data transfer.
    • Available only in Intel® Stratix® 10 and Intel® Agilex™ 7 E-tile device variations in current version of the Intel® Quartus® Prime software release.
      Note: Contact Intel Support to request Interlaken Look-aside mode access in IP variations that target an Intel® Stratix® 10 H- and L-tile device.
Table 1.  IP Supported Combinations of Number of Lanes and Data RatesThe following combinations are supported in the current version of the Intel® Quartus® Prime Pro Edition software.

Throughout this table, ILK refers to Interlaken mode and ILA refers to Interlaken Look-aside mode.

Device Supported Mode IP Supported Combinations
Number of Lanes Lane Rate (Gbps)1
L-tile ILK only 4 6.25
12.5
25.28
25.78
25.78125
8 12.5
12 10.3125
12.5
H-tile ILK only 4 6.25
12.5
25.28
25.78
25.78125
6 25.28
25.78
25.78125
8 12.5
25.28
25.78
25.78125
10 12.5
25.28
25.78
25.78125
12 10.3125
12.5
25.28
25.78
25.78125
E-tile (NRZ) ILK and ILA 4 6.25
12.5
25.28
25.78
25.78125
6 25.28
25.78
25.78125
8 12.5
25.28
25.78
25.78125
10 12.5
25.28
25.78
25.78125
12 10.3125
12.5
25.28
25.78
25.78125
E-tile (PAM4) ILK and ILA 12 26.56252
Table 2.  IP Theoretical Raw Aggregate BandwidthThe following combinations are supported in the current version of the Intel® Quartus® Prime Pro Edition software:
Number of Lanes Lane Rate (Gbps)
6.25 10.3125 12.5 25.28 25.78 25.78125 26.5625
4 25 - 50 101.12 103.12 103.125 -
6 - - - 151.68 154.68 154.6875 -
8 - - 100 202.24 206.24 206.25 -
10 - - 125 252.8 257.8 257.8125 -
12 - 123.75 150 303.36 309.36 309.375 318.75
1 You can customize the data rates depending on the tiles. Refer to the KDB for information on how to customize the data rate.
2 To obtain 6x53.125 Gbps speed in PAM4 mode, select 12x26.5625 Gbps.