Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

3.2. PMA Adaptation Parameters

After device configuration, you may need to trigger PMA adaptation on the RX interface to achieve optimal performance. The PMA interface performs adaptation for initial adaptation and continuous adaptation which runs continuously in background.
Figure 5. PMA Adaptation OptionsYou specify settings on the PMA Adaptation tab for both initial and continuous adaptation. PMA Adaptation is only available for E-tile variants.
Table 19.  PMA Adaptation
Parameter Value Description
Enable adaptation load soft IP On/Off Enables PMA adaptation parameter customization.
PMA adaptation select

PAM4_56Gbps_LR

PAM4_56Gbps_VSR

NRZ_28Gbps_LR

NRZ_28Gbps_VSR

NRZ_10Gbps_25/15/10dB

Selects pre-defined PMA configuration parameters.
Table 20.  Initial Adaptation Parameters
Parameter Value Description
GS1 Fw_default, 0, 1, 2, 3 CTLE Low Frequency Gain Shaping 1.
GS2 Fw_default, 0, 1, 2, 3 CTLE Low Frequency Gain Shaping 2.
RF_B1 Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8 RF_B1 Setting.
RF_B1 Fix/Adaptable Fixed, Adaptable RF_B1 Setting.
RF_B0 Fw_default, 0, 1, 2, 3, 4, 5 RF_B0 Setting.
RF_B0 Fix/Adaptable Fixed, Adaptable RF_B0 Setting.
RF_A Fw_default, 100, 110, 120, 130, 140, 150, 160 RF_A Setting.
GAINLF Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 CTLE Low Frequency Gain.
GAINLF Fixed/Adaptable Fixed, Adaptable CTLE Low Frequency Gain.
CTLE LF Min Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Limits CTLE LF minimum.
CTLE LF Max Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Limits CTLE LF maximum.
GAINHF Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Inputs CTLE High Frequency Gain.
GAINHF Fixed/Adaptable Fixed, Adaptable Inputs CTLE High Frequency Gain - Fix or Adaptable options.
CTLE HF Min Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Limits CTLE HF minimum.
CTLE HF Max Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Limits CTLE HF maximum.
RF_P2 Fw_default, -10, -9, -8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 RF_P2 setting.
RF_P2 Fixed/Adaptable Fixed, Adaptable RF_P2 setting - Fix or Adaptable options.
RF_P2 Min Fw_default, -10, -9, -8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 Limits RF_P2 minimum.
RF_P2 Max Fw_default, -10, -9, -8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 Limits RF_P2 maximum.
RF_P1 Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 RF_P1 setting.
RF_P1 Fixed/Adaptable Fixed, Adaptable RF_P1 setting - Fix or Adaptable options.
RF_P1 Min Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Limits RF_P1 minimum.
RF_P1 Max Fw_default, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Limits RF_P1 maximum.
RF_P0 Fw_default, -15, -14, -13, -12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Sets RF_P0.
RF_P0 Fixed/Adaptable Fixed, Adaptable Limits RF_P0 - Fix or Adaptable options.
RF_B0T Fw_default, 10, 15, 20, 25, 30, 35, 40, 45, 50 Controls the rate RF_B0 adapts.
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