Interlaken (2nd Generation) Intel® FPGA IP User Guide

Download PDF
ID 683396
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

5.1. Clock and Reset Interface Signals

Table 28.  Clock and Reset Interface Signals
Signal Name Feature Support Width (Bits) I/O Direction Description
pll_ref_clk / pll_ref_clk[1:0] 11 ILK and ILA 1/2 Input Transceiver reference clock for the RX CDR PLL in IP core variations that target a Intel® Stratix® 10 device. The sets of valid frequencies vary with the per-lane data rate of the transceivers as following:
Per-Lane Data Rate (Gbps) Valid pll_ref_clk Frequencies (MHz)
6.25 156.25, 195.3125, 250, 312.5, 390.625, 480.7692313, 500 12, 62512
10.3125 156.25, 206.25, 257.8125, 322.265625, 412.5, 491.07142813, 515.62512, 644.5312512
12.5 156.25, 195.3125, 250, 312.5, 390.625, 500, 62512
25.28 126.412, 158.0, 197.5, 252.8, 320.012, 395.0, 486.153846 13, 505.612
25.78 159.135802, 201.40625, 250.29126212, 322.25, 402.8125, 495.76923113, 500.58252412
25.78125 159.14351912, 159.14351813, 201.41601612, 201.41601513, 250.30339812, 322.265625, 402.832031, 500.60679612, 495.79326913
26.562514 156.25, 210.813492, 312.5, 390.625, 491.898148
Note: pll_ref_clk[1] is only available when you enable Preserve unused transceiver channels for PAM4 parameter in E-tile PAM4 mode IP variations.
tx_usr_clk ILK only 1 Input Transmit side user data interface clock. The lower frequency of tx_usr_clk increases the latency of data path.
rx_usr_clk ILK only 1 Input Receive side user data interface clock. The lower frequency of rx_usr_clk increases the latency of data path.
clk_tx_common ILK and ILA 1 Output Transmit PCS common lane clock driven by the SERDES transmit PLL.
The frequency is given by the following equation: 
Frequency of clk_tx_common = transceiver data rate / PMA_WIDTH
For example, the clock rate is 322 MHz at 10.3125 Gbps transceiver speed with 32 bits.
The valid frequencies per lane data rate are as below:
Data Rate (Gbps) E-tile L- and H-tile
PMA_WIDTH clk_tx_common PMA_WIDTH clk_tx_common
6.25 64 97.656250 32 195.3125
10.3125 64 161.132813 32 (For number of segments = 1) 322.265625
64 (For number of segments = 2) 161.1328125
12.5 64 195.3125 64 195.3125
40 (Only for number of segments =1 and 12x12.5 Gbps combination) 312.5
25.28 64 395.0 64 395.0
25.78 64 402.8125 64 402.8125
25.78125 64 402.8320 64 402.8320
26.5625 64 415.039063 N/A N/A
clk_rx_common ILK and ILA 1 Output Receive PCS common lane clock driven by CDR in transceiver.
The frequency is given by the following equation: 
Frequency of clk_rx_common = transceiver data rate / PMA_WIDTH
For example, the clock rate is 322 MHz at 10.3125 Gbps transceiver speed with 32 bits PMA_WIDTH. The valid frequencies for clk_rx_common are same as clk_tx_common.
reset_n ILK and ILA 1 Input Active-low asynchronous reset signal.
tx_usr_srst ILK and ILA 1 Output Transmit-side reset output signal. Indicates the transmit side user data interface is resetting. This signal is synchronous with tx_usr_clk.
rx_usr_srst ILK and ILA 1 Output Receive-side reset output. Indicates the receive side user data interface is resetting. This signal is synchronous with rx_usr_clk.
mac_clkin ILK and ILA 1 Input This clock signal is only available in IP core variations that target an E-tile PAM4 device variations. This signal must be driven by a PLL and must use the same clock source that drives the pll_ref_clk.
Related Information
11 When you enable Preserve unused transceiver channels for PAM4 parameter, an additional reference clock port is added to preserve the unused PAM4 slave channel.
12 Only available in H-tile and L-tile device variations.
13 Only available in NRZ E-tile device variations.
14 Only available in PAM4 E-tile device variations.
Level Two Title