F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 11/03/2023
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Limitation 2.1.3. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Application (APPS) 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Application (APPS) x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. SR-IOV Design Example Limitation 2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. SR-IOV Applications (APPS)
2.2.1.2. SR-IOV Applications (APPS) x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Installing the Linux Kernel Driver 3.7. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Steps to Run Simulation 3.3.2. Testbench
3.3.1. Steps to Run Simulation x
3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : QuestaSim* / ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition 3.3.1.4. Steps to Run Simulation : Xcelium* 3.3.1.5. Steps to Run Simulation : Riviera-PRO*
3.3.2. Testbench x
3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench
3.7. Running the Design Example x
3.7.1. Running the PIO Design Example 3.7.2. Running the SR-IOV Design Example 3.7.3. Running the Performance Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

3.3.2.4. Performance Design Example Testbench

The figure below shows the Performance design example simulation design hierarchy. The tests for the Performance design example are defined with the apps_type_hwtcl parameter set to 3. The tests run under this parameter value are defined in ebfm_cfg_rp_ep_rootport, find_mem_bar and perf_ed_dma_write/perf_ed_dma_read.

Figure 25. Performance Design Example Simulation Design Hierarchy
The testbench starts with link training and then accesses the configuration space of the IP for enumeration. A task called perf_ed_dma_write and perf_ed_dma_read (defined in the Root Port PCIe BFM altpcietb_bfm_rp_gen4_x16.sv) then performs the PCIe link test. This test consists of the following steps:
  1. Issue a memory write command to set up the Performance design example's target memory write address.
  2. Issue a memory write command to trigger the Performance design example to send 10 memory writes with 128 bytes in length.
  3. Issue a memory write command to set up the Performance design example's target memory read address.
  4. Issue a memory write command to trigger the Performance design example to send 10 memory reads with 128 bytes in length.

The first memory write takes place around 208 µs. The 10 memory writes and 10 memory reads with completions from the RP BFM appear shortly after the memory write requests at the Avalon-ST RX interface.

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