F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 4/27/2023
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example
2.1. Programmed Input/Output Design Example x
2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Simulation Testbench
2.1.1. Programmed Input/Output Design Example Functional Description x
2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Application (APPS) 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP
2.1.1.2. PIO Application (APPS) x
2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter
2.2. Single Root I/O Virtualization (SR-IOV) Design Example x
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. SR-IOV Applications (APPS)
2.2.1.2. SR-IOV Applications (APPS) x
2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP
2.3. Performance Design Example x
2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Installing the Linux Kernel Driver 3.7. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Steps to Run Simulation 3.3.2. Testbench
3.3.1. Steps to Run Simulation x
3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : QuestaSim* / ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition 3.3.1.4. Steps to Run Simulation : Xcelium*
3.3.2. Testbench x
3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench
3.7. Running the Design Example x
3.7.1. Running the PIO Design Example 3.7.2. Running the SR-IOV Design Example 3.7.3. Running the Performance Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.04.27 23.1 8.1.0
2023.02.03 22.4 8.0.0 Added requirements for the reference clock for the System PLL to the F-Tile Reference and System PLL Clocks IP section.
2022.10.04 22.3 7.0.0
Sections Updated:
  • Design Example Description: New column Hardware added in table F-Tile Avalon-ST IP Design Examples
  • Generating the Design Example: Step 11(c) updated
  • Simulating the Design Example: Command updated for FASTSIM mode for VCS simulator in Steps to Run Simulation table
  • Hardware and Software Requirements: All contents updated
  • Running the SR-IOV Design Example: Steps (5) and (6) updated
  • Running the Performance Design Example: Note added about 500 MHz hardware test support
  • Running the Performance Design Example: Step (7) added
  • Running the Performance Design Example: Figures illustrating Write, Read, Simultaneous Write and Read operations added
  • Running the Performance Design Example: Test Results updated for Write, Read, Simultaneous Write and Read operations
  • Running the Performance Design Example: Performance Design Example Data Throughput information added
2022.07.14 22.2 6.0.0
  • Design Example Description: F-Tile Avalon-ST IP Design Examples table updated
  • Performance Design Example: New design example information added
  • Generating Design Example: Step 11c added & Example Designs Tab GUI screenshot updated
  • Simulating the Design Example: Commands updated for all simulators in Steps to Run Simulation table
  • Performance Design Example Testbench: New section added
  • Hardware and Software Requirements: New section added
  • Installing the Linux Kernel Driver: Introductory description modified
  • Running the Design Example: Test Operations Supported by the F-Tile Avalon-ST IP for PCI Express Design Examples table reorganized and updated
  • Running the PIO Design Example: GUI screenshots for sample transcripts for automatic and manual modes updated
  • Running the SR-IOV Design Example: Link Test Menu GUI screenshot updated
  • Running the Performance Design Example: New section added
2021.12.17 21.4 4.0.0
  • SR-IOV Design Example related information added to Design Example Description chapter
  • SR-IOV Design Example related information added to Quick Start Guide chapter
  • Generating tile files information added to Quick Start Guide chapter
  • Xcelium simulator information added to Steps to run simulation table
  • Running the SR-IOV Design Example section added to Quick Start Guide chapter
2021.10.04 21.3 3.0.0
  • Updated Configurations Supported by the F-Tile Avalon-ST Design Examples Table
  • Added PCIe Gen3/Gen4 x8 Design Example Variant block diagram
  • Added PIO Application (APPS) component information in Functional Description
  • Added Block Diagram for the PCIe x8 PIO Design Example Simulation Testbench block diagram
  • Added Platform Designer System Contents for F-Tile Avalon®-ST IP for PCI Express PIO Design Example Gen4 x8 variant screenshot
  • Update figure Directory Structure for the Generated Design Example
  • Procedure updated in Simulating the Design Example
  • Added VCSMX simulator information to Steps to Run Simulation table.
2021.07.31 21.2 2.0.0 Initial Release
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