Hyperflex® Architecture High-Performance Design Handbook

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ID 683353
Date 12/06/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Hyperflex® FPGA Architecture Introduction 2. Hyperflex® Architecture RTL Design Guidelines 3. Compiling Hyperflex® Architecture Designs 4. Design Example Walk-Through 5. Retiming Restrictions and Workarounds 6. Optimization Example 7. Hyperflex® Architecture Porting Guidelines 8. Appendices 9. Hyperflex® Architecture High-Performance Design Handbook Archive 10. Hyperflex® Architecture High-Performance Design Handbook Revision History
1. Hyperflex® FPGA Architecture Introduction x
1.1. Hyperflex® Architecture Design Concepts
2. Hyperflex® Architecture RTL Design Guidelines x
2.1. High-Speed Design Methodology 2.2. Hyper-Retiming (Facilitate Register Movement) 2.3. Hyper-Pipelining (Add Pipeline Registers) 2.4. Hyper-Optimization (Optimize RTL)
2.1. High-Speed Design Methodology x
2.1.1. Set a High-Speed Target 2.1.2. Experiment and Iterate 2.1.3. Compile Components Independently 2.1.4. Optimize Sub-Modules 2.1.5. Avoid Broadcast Signals
2.1.1. Set a High-Speed Target x
2.1.1.1. Speed and Timing Closure 2.1.1.2. Speed and Latency
2.2. Hyper-Retiming (Facilitate Register Movement) x
2.2.1. Reset Strategies 2.2.2. Clock Enable Strategies 2.2.3. Preserving Registers During Synthesis 2.2.4. Timing Constraint Considerations 2.2.5. Clock Synchronization Strategies 2.2.6. Metastability Synchronizers 2.2.7. Initial Power-Up Conditions 2.2.8. Retiming through RAMs and DSPs
2.2.1. Reset Strategies x
2.2.1.1. Removing Asynchronous Resets 2.2.1.2. Synchronous Resets on Global Clock Trees 2.2.1.3. Synchronous Resets on I/O Ports 2.2.1.4. Duplicate and Pipeline Synchronous Resets
2.2.2. Clock Enable Strategies x
2.2.2.1. Localized Clock Enable 2.2.2.2. High Fan-Out Clock Enable 2.2.2.3. Clock Enable with Timing Exceptions
2.2.4. Timing Constraint Considerations x
2.2.4.1. Optimize Multicycle Paths 2.2.4.2. Overconstraints
2.2.5. Clock Synchronization Strategies x
2.2.5.1. Clock Domain Crossing Constraint Guidelines
2.2.7. Initial Power-Up Conditions x
2.2.7.1. Specifying Initial Memory Conditions 2.2.7.2. Initial Conditions and Retiming 2.2.7.3. Initial Conditions and Hyper-Registers 2.2.7.4. Retiming Reset Sequences
2.2.7.3. Initial Conditions and Hyper-Registers x
2.2.7.3.1. Implementing Clock Gating 2.2.7.3.2. Quartus® Prime Settings for Initial Conditions
2.3. Hyper-Pipelining (Add Pipeline Registers) x
2.3.1. Conventional Versus Hyper-Pipelining 2.3.2. Pipelining and Latency 2.3.3. Use Registers Instead of Multicycle Exceptions
2.3.2. Pipelining and Latency x
2.3.2.1. Pipelining at Variable Latency Locations 2.3.2.2. Automatic Pipeline Insertion
2.3.2.1. Pipelining at Variable Latency Locations x
2.3.2.1.1. Specifying a Latency-Insensitive False Path
2.3.2.2. Automatic Pipeline Insertion x
2.3.2.2.1. Step 1: Create the Variable Latency Module 2.3.2.2.2. Step 2: Instantiate the Variable Latency Module 2.3.2.2.3. Step 3: Verify Automatic Pipeline Insertion Option 2.3.2.2.4. (Optional) Auto-Pipeline Insertion without a Variable Latency Module
2.4. Hyper-Optimization (Optimize RTL) x
2.4.1. General Optimization Techniques 2.4.2. Optimizing Specific Design Structures
2.4.1. General Optimization Techniques x
2.4.1.1. Shannon’s Decomposition 2.4.1.2. Time Domain Multiplexing 2.4.1.3. Loop Unrolling 2.4.1.4. Loop Pipelining 2.4.1.5. Precomputation
2.4.1.1. Shannon’s Decomposition x
2.4.1.1.1. Shannon’s Decomposition Example 2.4.1.1.2. Identifying Circuits for Shannon’s Decomposition
2.4.1.4. Loop Pipelining x
2.4.1.4.1. Loop Pipelining Theory 2.4.1.4.2. Loop Pipelining Demonstration 2.4.1.4.3. Loop Pipelining and Synthesis Optimization
2.4.2. Optimizing Specific Design Structures x
2.4.2.1. High-Speed Clock Domains 2.4.2.2. Restructuring Loops 2.4.2.3. Control Signal Backpressure 2.4.2.4. Flow Control with FIFO Status Signals 2.4.2.5. Flow Control with Skid Buffers 2.4.2.6. Read-Modify-Write Memory 2.4.2.7. Counters and Accumulators 2.4.2.8. State Machines 2.4.2.9. Memory 2.4.2.10. DSP Blocks 2.4.2.11. General Logic 2.4.2.12. Modulus and Division 2.4.2.13. Resets 2.4.2.14. Hardware Re-use 2.4.2.15. Algorithmic Requirements 2.4.2.16. FIFOs 2.4.2.17. Ternary Adders
2.4.2.1. High-Speed Clock Domains x
2.4.2.1.1. Visualizing Clock Networks 2.4.2.1.2. Viewing Clock Networks in the Fitter Report 2.4.2.1.3. Viewing Clocks in the Timing Analyzer
2.4.2.9. Memory x
2.4.2.9.1. Hyperflex® Architecture True Dual-Port Memory 2.4.2.9.2. Use Simple Dual-Port Memories 2.4.2.9.3. Hyperflex® Architecture Simple Dual-Port Memory Example 2.4.2.9.4. Memory Mixed Port Width Ratio Limits Top-Level Descramble RTL Code Supporting RTL Code 2.4.2.9.5. Unregistered RAM Outputs
3. Compiling Hyperflex® Architecture Designs x
3.1. Compiling Submodules Independently 3.2. Design Assistant Design Rule Checking
3.2. Design Assistant Design Rule Checking x
3.2.1. Running Design Assistant During Compilation 3.2.2. Running Design Assistant in Analysis Mode
3.2.2. Running Design Assistant in Analysis Mode x
3.2.2.1. Cross-Probing from Design Assistant to Visualization Tools 3.2.2.2. Launching Design Assistant from Chip Planner 3.2.2.3. Launching Design Assistant from Timing Analyzer
4. Design Example Walk-Through x
4.1. Median Filter Design Example
4.1. Median Filter Design Example x
4.1.1. Step 1: Compile the Base Design 4.1.2. Step 2: Add Pipeline Stages and Remove Asynchronous Resets 4.1.3. Step 3: Add More Pipeline Stages and Remove All Asynchronous Resets 4.1.4. Step 4: Optimize Short Path and Long Path Conditions
5. Retiming Restrictions and Workarounds x
5.1. Setting the dont_merge Synthesis Attribute 5.2. Interpreting Critical Chain Reports
5.2. Interpreting Critical Chain Reports x
5.2.1. Insufficient Registers 5.2.2. Short Path/Long Path 5.2.3. Fast Forward Limit 5.2.4. Loops 5.2.5. One Critical Chain per Clock Domain 5.2.6. Critical Chains in Related Clock Groups 5.2.7. Complex Critical Chains 5.2.8. Extend to locatable node 5.2.9. Domain Boundary Entry and Domain Boundary Exit 5.2.10. Critical Chains with Dual Clock Memories 5.2.11. Critical Chain Bits and Buses 5.2.12. Delay Lines
5.2.1. Insufficient Registers x
5.2.1.1. Insufficient Registers Example 5.2.1.2. Optimizing Insufficient Registers 5.2.1.3. Critical Chains with Dual Clock Memories
5.2.2. Short Path/Long Path x
5.2.2.1. Hyper-Register Locations Not Available 5.2.2.2. Example for Hold Optimization 5.2.2.3. Optimizing Short Path/Long Path 5.2.2.4. Add Registers 5.2.2.5. Duplicate Common Nodes 5.2.2.6. Data and Control Plane
5.2.3. Fast Forward Limit x
5.2.3.1. Optimizing Path Limit
5.2.4. Loops x
5.2.4.1. Example of Loops Limiting the Critical Chain
6. Optimization Example x
6.1. Round Robin Scheduler
7. Hyperflex® Architecture Porting Guidelines x
7.1. Design Migration and Performance Exploration 7.2. Top-Level Design Considerations
7.1. Design Migration and Performance Exploration x
7.1.1. Black-boxing Verilog HDL Modules 7.1.2. Black-boxing VHDL Modules 7.1.3. Clock Management 7.1.4. Pin Assignments 7.1.5. Transceiver Control Logic 7.1.6. Upgrade Outdated IP Cores
8. Appendices x
8.1. Appendix A: Parameterizable Pipeline Modules 8.2. Appendix B: Clock Enables and Resets
8.2. Appendix B: Clock Enables and Resets x
8.2.1. Synchronous Resets and Limitations 8.2.2. Retiming with Clock Enables 8.2.3. Resolving Short Paths
8.2.1. Synchronous Resets and Limitations x
8.2.1.1. Synchronous Resets Summary
8.2.2. Retiming with Clock Enables x
8.2.2.1. Example for Broadcast Control Signals
Answers to Top FAQs
1. Hyperflex® FPGA Architecture Introduction
2. Hyperflex® Architecture RTL Design Guidelines
3. Compiling Hyperflex® Architecture Designs
4. Design Example Walk-Through
5. Retiming Restrictions and Workarounds
6. Optimization Example
7. Hyperflex® Architecture Porting Guidelines
8. Appendices
9. Hyperflex® Architecture High-Performance Design Handbook Archive
10. Hyperflex® Architecture High-Performance Design Handbook Revision History

2.4.2.9.4. Memory Mixed Port Width Ratio Limits

Hyperflex® architecture FPGA device block RAMs enable clocks speeds of up to 1GHz. The new RAM block design is more restrictive with respect to use of mixed ports data width. Hyperflex® architecture FPGA device block RAMs do not support 1/32, 1/16, or 1/8 mixed port ratios. The only valid ratios are 1, ½, and ¼ mixed port ratios. The Compiler generates an error message for implementation of invalid mixed port ratios.

When migrating a design that uses invalid port width ratios for Hyperflex® architecture FPGAs, modify the RTL to create the desired ratio.

Figure 79. Dual-Port Memory with Invalid 1/8 Mixed Port Ratio

To create a functionally equivalent design, create and combine smaller memories with valid mixed port width ratios. For example, the following steps implement a mixed port width ratio:

  1. Create two memories with ¼ mixed port width ratio by instantiating the 2-Ports memory IP core from the IP Catalog.
  2. Define write enable logic to ping-pong writing between the two memories.
  3. Interleave the output of the memories to rebuild a 1/8 ratio output.
Figure 80. 1/8 Width Ratio Example

This example shows the interleaving of two memories and the write logic. The chosen write logic uses the least significant bit of the write address to decide which memory to write. Even addresses write in memory mem_A, odd addresses write in memory mem_B.

Because of the scheme that controls writing to the memories, carefully reconstruct the full 64-bit output during a write. You must account for the interleaving of the individual 8-bit words in the two memories.

Figure 81. Memory Output Descrambling Example

This example shows the descrambled output when attempting to read at address 0h0.

The following RTL examples implement the extra stage to descramble the data from memory on the read side.

Top-Level Descramble RTL Code

module test 
#(	parameter WR_DATA_WIDTH = 8,
		parameter RD_DATA_WIDTH = 64,
		parameter WR_DEPTH = 64,
		parameter RD_DEPTH = 4,
		parameter WR_ADDR_WIDTH = 6,
		parameter RD_ADDR_WIDTH = 4
)(
	data, wraddress, rdaddress,	wren,
	wrclock, rdclock,	q
);

input	[WR_DATA_WIDTH-1:0]	data;
input	[WR_ADDR_WIDTH-1:0]	wraddress;
input	[RD_ADDR_WIDTH-1:0]	rdaddress;
input		wren;
input		wrclock;
input		rdclock;
output	[RD_DATA_WIDTH-1:0]	q;

wire wrena, wrenb;
wire [(RD_DATA_WIDTH/2)-1:0] q_A, q_B;

memorySelect memWriteSelect (
	.wraddress_lsb(wraddress[0]),
	.wren(wren),
	.wrena(wrena),
	.wrenb(wrenb)
);

myMemory mem_A (
	.data(data),
	.wraddress(wraddress),
	.rdaddress(rdaddress),
	.wren(wrena),
	.wrclock(wrclock),
	.rdclock(rdclock),
	.q(q_A)
);

myMemory mem_B (
	.data(data),
	.wraddress(wraddress),
	.rdaddress(rdaddress),
	.wren(wrenb),
	.wrclock(wrclock),
	.rdclock(rdclock),
	.q(q_B)
);

descrambler #(
	.WR_WIDTH(WR_DATA_WIDTH),
	.RD_WIDTH(RD_DATA_WIDTH)
) outputDescrambler (
	.qA(q_A),
	.qB(q_B),
	.qDescrambled(q)
);

endmodule

Supporting RTL Code

module memorySelect (wraddress_lsb, wren, wrena, wrenb);
	input wraddress_lsb;
	input wren;
	output wrena, wrenb;

	assign wrena = !wraddress_lsb && wren;
	assign wrenb = wraddress_lsb && wren;
endmodule

module descrambler #(
	parameter WR_WIDTH = 8,
	parameter RD_WIDTH = 64
) (
	input [(RD_WIDTH/2)-1 : 0] qA,
	input [(RD_WIDTH/2)-1 : 0] qB,
	output [RD_WIDTH:0] qDescrambled
);

	genvar i;
	generate
  	for (i=WR_WIDTH*2; i<=RD_WIDTH; i += WR_WIDTH*2) begin: descramble
   	  assign qDescrambled[i-WR_WIDTH-1:i-(WR_WIDTH*2)] = qA[(i/2)-1:(i/2)-WR_WIDTH];
      assign qDescrambled[i-1:i-WR_WIDTH] = qB[(i/2)-1:(i/2)-WR_WIDTH];
    end
  endgenerate

endmodule
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