Visible to Intel only — GUID: rrf1496420468099
Ixiasoft
1. Discontinuation of the Intel® HLS Compiler
2. Intel® HLS Compiler Pro Edition Reference Manual
3. Compiler
4. C Language and Library Support
5. Component Interfaces
6. Component Memories (Memory Attributes)
7. Loops in Components
8. Component Concurrency
9. Arbitrary Precision Math Support
10. Component Target Frequency
11. Systems of Tasks
12. Libraries
13. Advanced Hardware Synthesis Controls
14. Intel® High Level Synthesis Compiler Pro Edition Reference Summary
A. Advanced Math Source Code Libraries
B. Supported Math Functions
C. Cyclone® V Restrictions
D. Intel® HLS Compiler Pro Edition Reference Manual Archives
E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual
15. Discontinuation of the Intel® HLS Compiler
7.1. Loop Initiation Interval (ii Pragma)
7.2. Loop-Carried Dependencies (ivdep Pragma)
7.3. Loop Coalescing (loop_coalesce Pragma)
7.4. Loop Unrolling (unroll Pragma)
7.5. Loop Concurrency (max_concurrency Pragma)
7.6. Loop Iteration Speculation (speculated_iterations Pragma)
7.7. Loop Pipelining Control (disable_loop_pipelining Pragma)
7.8. Loop Interleaving Control (max_interleaving Pragma)
7.9. Loop Fusion
12.4.1.1. Integration of an RTL Module into the HLS Pipeline
12.4.1.2. RTL Module Interfaces
12.4.1.3. RTL Reset and Clock Signals
12.4.1.4. Object Manifest File Syntax
12.4.1.5. Mapping HLS Data Types to RTL Signals
12.4.1.6. HLS Emulation Models for RTL-Based Functions
12.4.1.7. Potential Incompatibility between RTL Modules and Partial Reconfiguration
12.4.1.8. Stall-Free RTL
12.4.1.9. RTL Module Restrictions and Limitations for HLS Libraries
14.1. Intel® HLS Compiler Pro Edition i++ Command-Line Arguments
14.2. Intel® HLS Compiler Pro Edition Header Files
14.3. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
14.4. Intel® HLS Compiler Pro Edition Keywords
14.5. Intel® HLS Compiler Pro Edition Simulation API (Testbench Only)
14.6. Intel® HLS Compiler Pro Edition Component Memory Attributes
14.7. Intel® HLS Compiler Pro Edition Loop Pragmas
14.8. Intel® HLS Compiler Pro Edition Scope Pragmas
14.9. Intel® HLS Compiler Pro Edition Component Attributes
14.10. Intel® HLS Compiler Pro Edition Component Default Interfaces
14.11. Intel® HLS Compiler Pro Edition Component Invocation Interface Control Attributes
14.12. Intel® HLS Compiler Pro Edition Component Macros
14.13. Intel® HLS Compiler Pro Edition Systems of Tasks API
14.14. Intel® HLS Compiler Pro Edition Pipes API
14.15. Intel® HLS Compiler Pro Edition Streaming Input Interfaces
14.16. Intel® HLS Compiler Pro Edition Streaming Output Interfaces
14.17. Intel® HLS Compiler Pro Edition Memory-Mapped Interfaces
14.18. Intel® HLS Compiler Pro Edition Load-Store Unit Control
14.19. Intel® HLS Compiler Pro Edition Arbitrary Precision Data Types
B.1. Math Functions Provided by the math.h Header File
B.2. Math Functions Provided by the extendedmath.h Header File
B.3. Math Functions Provided by the ac_fixed_math.h Header File
B.4. Math Functions Provided by the hls_float.h Header File
B.5. Math Functions Provided by the hls_float_math.h Header File
B.6. Default Rounding Schemes and Subnormal Number Support
Visible to Intel only — GUID: rrf1496420468099
Ixiasoft
7.5. Loop Concurrency (max_concurrency Pragma)
You can use the max_concurrency pragma to increase or limit the concurrency of a loop in your component. The concurrency of a loop is how many iterations of that loop can be in progress at one time. By default, the Intel® HLS Compiler tries to maximize the concurrency of loops so that your component runs at peak throughput.
To achieve maximum concurrency in loops, sometimes private copies of component memory have to be created to break dependencies on the underlying hardware that prevent the loop from being fully pipelined.
You can see the number of private copies created for you component memories in the High-Level Design reports (report.html) for your component:
- In the Details pane of the Loop Analysis report as a message that says that the maximum number of simultaneous executions has been limited to N.
- In the Bank view of your component memory in the Function Memory Viewer, which graphically shows the number of private copies.
If you want to exchange some performance for component memory savings, apply #pragma max_concurrency <N> to the loop. When you apply this pragma, the number of private copies changes and controls the number of iterations entering the loop, as shown in the following example:
#pragma max_concurrency 1 for (int i = 0; i < N; i++) { int arr[M]; // Doing work on arr }
You can control the number of private copies created for a component memory accessed withing a loop by using the hls_private_copies memory attribute. For details, see hls_private_copies Memory Attribute. For an example of increasing the number of private copies of memory, refer to the following tutorial:
<quartus_installdir>/hls/examples/tutorials/component_memories/non_power_of_two_memory
You can also control the concurrency of your component by using the hls_max_concurrency component attribute. For more information about the hls_max_concurrency(N) component attribute, see Concurrency Control (hls_max_concurrency Attribute). For an example increasing concurrency for better throughput, refer to the following tutorial:
<quartus_installdir>/hls/examples/tutorials/best_practices/optimize_ii_using_hls_register