DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 9/30/2024
Public
Document Table of Contents

14.6.6.5. Specifying ForLoop Control Units

The DSP Builder Finite State Machine block is a convenient way to construct control logic using one or more ForLoop blocks.
Figure 148. ForLoop Control UnitThe figure shows a ForLoop block that starts counting from 0 to 9 in increments of 1.

Procedure

  1. Add the following code to the .fsm file to generates an equivalent ForLoop block:
        # Example for-loop
        require version 23.3
        enable en
        netlist
        for x 0 < 10 : ld v c
        end
    
    1. Specify the enable keyword when you want to expose the enable input of the ForLoop block as an input port on the Finite State Machine block.
      The ls (loop-start) input on the first ForLoop defined in the .fsm configuration file is always connected to the go input of the Finite State Machine block.
    2. List the output ports of the ForLoop block that you expose as output ports on the Finite State Machine block after a colon following the for definition.
  2. Specify a step or counter increment, which is necessary when specifying decrementing counters:
        # Example of a decrementing for-loop
        require version 23.3
        enable en
        netlist
        for x 5 >= -5 step -2 : ld v c
        end