Visible to Intel only — GUID: hco1423077121804
Ixiasoft
Visible to Intel only — GUID: hco1423077121804
Ixiasoft
14.4.8. Bit Combine (BitCombine)
((h << bitwidth(i)) | i)
You can change the number of inputs on the BitCombine block according to your requirements. When Boolean vectors are input on multiple ports, DSP Builder combines corresponding components from each vector and outputs a vector of signals. The widths of all input vectors must match. However, the widths of the signals arriving on different inputs do not have to be equal. The one input BitCombine block is a special case that concatenates all the components of the input vector, so that one wide scalar signal is output. Use with logical operators to apply a 1-bit reducing operator to Boolean vectors.
If all inputs on all ports are complex signals, DSP Builder applies the bit combine operation to the real part and imaginary parts component by component. DSP Builder does not concatenate the real and imaginary parts.
If the inputs on multiple ports are a mixture of real and complex signals, DSP Builder converts the real values to complex values that have zero padded imaginary parts. DSP Builder then concatenates the imaginary parts of all inputs as before.
Parameter | Description |
---|---|
Number of inputs | Specifies the number of inputs. |
Output data type mode | Determines how the block sets its output data type:
|
Output data type | Specifies the output data type. For example, sfix(16), uint(8). |
Output scaling value | Specifies the output scaling value. For example, 2^-15. |
Signal | Direction | Type | Description | Vector Data Support | Complex Data Support |
---|---|---|---|---|---|
i | Input | Any fixed-point type | Operand | Yes | Yes |
h | Input | Any fixed-point type | Operand | Yes | Yes |
q | Output | Derived fixed-point type | Result | Yes | Yes |