DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

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ID 683337
Date 5/01/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About DSP Builder for Intel® FPGAs 3. DSP Builder for Intel FPGAs Advanced Blockset Getting Started 4. DSP Builder Design Flow 5. Primitive Library Blocks Tutorial 6. IP Tutorial 7. DSP Builder for Intel FPGAs (Advanced Blockset) Design Examples and Reference Designs 8. DSP Builder Design Rules, Design Recommendations, and Troubleshooting 9. About DSP Builder for Intel FPGAs Optimization 10. About Folding 11. Floating-Point Data Types 12. Design Configuration Library 13. IP Library 14. Interfaces Library 15. Primitives Library 16. Utilities Library 17. Simulink Supported Blocks 18. Document Revision History for DSP Builder for Intel FPGAs (Advanced Blockset) Handbook
2. About DSP Builder for Intel® FPGAs x
2.1. DSP Builder for Intel® FPGAs Features 2.2. DSP Builder for Intel® FPGAs Design Structure 2.3. DSP Builder for Intel® FPGAs Libraries 2.4. DSP Builder for Intel® FPGAs Device Support 2.5. FPGA Architecture Features for DSP Designs 2.6. DSP Design Flow in FPGAs 2.7. Software and Hardware DSP Design Flows in FPGAs
3. DSP Builder for Intel FPGAs Advanced Blockset Getting Started x
3.1. Installing DSP Builder for Intel® FPGAs 3.2. Licensing DSP Builder for Intel® FPGAs 3.3. Starting DSP Builder in MATLAB* 3.4. Browsing DSP Builder Libraries and Adding Blocks to a New Model 3.5. Browsing and Opening DSP Builder Design Examples 3.6. Creating a New DSP Builder Design with the DSP Builder New Model Wizard 3.7. Simulating, Verifying, Generating, and Compiling Your DSP Builder Design
3.6. Creating a New DSP Builder Design with the DSP Builder New Model Wizard x
3.6.1. DSP Builder Menu Options 3.6.2. DSP Builder New Model Wizard Setup Script Parameters
4. DSP Builder Design Flow x
4.1. Implementing your Design in DSP Builder Advanced Blockset 4.2. Verifying your DSP Builder Advanced Blockset Design in Simulink and MATLAB 4.3. Exploring DSP Builder Advanced Blockset Design Tradeoffs 4.4. Verifying your DSP Builder Design with C++ Software Models 4.5. Verifying your DSP Builder Advanced Blockset Design in the ModelSim Simulator 4.6. Verifying Your DSP Builder Design in Hardware 4.7. Integrating Your DSP Builder Advanced Blockset Design into Hardware
4.1. Implementing your Design in DSP Builder Advanced Blockset x
4.1.1. Dividing your DSP Builder Design into Subsystems 4.1.2. Connecting DSP Builder Subsystems 4.1.3. Creating a New Design by Copying a DSP Builder Design Example 4.1.4. Vectorized Inputs
4.1.2. Connecting DSP Builder Subsystems x
4.1.2.1. DSP Builder Block Interface Signals 4.1.2.2. Periods 4.1.2.3. Sample Rate 4.1.2.4. Building Multichannel Systems 4.1.2.5. Channelization for Two Channels with a Folding Factor of 3 4.1.2.6. Channelization for Four Channels with a Folding Factor of 3 4.1.2.7. Synchronization and Scheduling of Data with the Channel Signal 4.1.2.8. Simulink vs Hardware Design Representations
4.1.2.1. DSP Builder Block Interface Signals x
4.1.2.1.1. Multichannel Systems with IP Library Blocks 4.1.2.1.2. Valid, Channel, and Data Examples
4.1.2.4. Building Multichannel Systems x
4.1.2.4.1. Multichannel Systems with IP Library Blocks
4.1.3. Creating a New Design by Copying a DSP Builder Design Example x
4.1.3.1. Creating a New Design From the DSP Builder FIR Design Example and Changing the Namespaces
4.2. Verifying your DSP Builder Advanced Blockset Design in Simulink and MATLAB x
4.2.1. Verifying your DSP Builder Advanced Blockset Design with a Testbench 4.2.2. Running DSP Builder Advanced Blockset Automatic Testbenches 4.2.3. Using DSP Builder Advanced Blockset References 4.2.4. Setting Up Stimulus in DSP Builder Advanced Blockset 4.2.5. Analyzing your DSP Builder Advanced Blockset Design
4.2.1. Verifying your DSP Builder Advanced Blockset Design with a Testbench x
4.2.1.1. Visualization Features
4.2.2. Running DSP Builder Advanced Blockset Automatic Testbenches x
4.2.2.1. dspba.runModelsimATB 4.2.2.2. Running All Automatic Testbenches 4.2.2.3. The command run_all_atbs Command Syntax 4.2.2.4. Testbench Error Messages
4.3. Exploring DSP Builder Advanced Blockset Design Tradeoffs x
4.3.1. Bit Growth 4.3.2. Managing Bit Growth in DSP Builder Advanced Blockset Designs 4.3.3. Using Rounding and Saturation in DSP Builder Advanced Blockset Designs 4.3.4. Scaling with Primitive Blocks 4.3.5. Changing Data Type with Convert Blocks and Specifying Output Types
4.3.5. Changing Data Type with Convert Blocks and Specifying Output Types x
4.3.5.1. The Convert Block and Real-world Values 4.3.5.2. Output Data Types on Primitive Blocks
4.4. Verifying your DSP Builder Design with C++ Software Models x
4.4.1. Software Model Options 4.4.2. Software Model Generated Files 4.4.3. Software Model Compilers 4.4.4. Compiling Testbenches and Model Libraries 4.4.5. Testing the Software Model 4.4.6. MATLAB MEX Function Wrapper for a Generated Software Model
4.4.5. Testing the Software Model x
4.4.5.1. Linking to External Libraries
4.4.6. MATLAB MEX Function Wrapper for a Generated Software Model x
4.4.6.1. Driving the Model 4.4.6.2. MEX Model Code 4.4.6.3. Complete the MEX Function 4.4.6.4. Compile, Run, and Test the MEX Function
4.5. Verifying your DSP Builder Advanced Blockset Design in the ModelSim Simulator x
4.5.1. Automatic Testbench 4.5.2. DSP Builder Advanced Blockset ModelSim Simulations
4.5.1. Automatic Testbench x
4.5.1.1. DSP Builder Advanced Blockset Automatic Testbench Files
4.6. Verifying Your DSP Builder Design in Hardware x
4.6.1. Hardware Verification
4.6.1. Hardware Verification x
4.6.1.1. Hardware Verification Design Example
4.7. Integrating Your DSP Builder Advanced Blockset Design into Hardware x
4.7.1. DSP Builder Generated Files 4.7.2. DSP Builder Designs and the Quartus Prime Project 4.7.3. Interfaces with a Processor Bus 4.7.4. DSP Builder Designs in Platform Designer
4.7.2. DSP Builder Designs and the Quartus Prime Project x
4.7.2.1. Adding a DSP Builder Advanced Blockset Design to an Existing Quartus Prime Project
4.7.3. Interfaces with a Processor Bus x
4.7.3.1. Assigning Base Addresses in DSP Builder Designs 4.7.3.2. Updating Registers with the Nios II Processor
4.7.4. DSP Builder Designs in Platform Designer x
4.7.4.1. Integrating a DSP Builder Design to a Platform Designer System 4.7.4.2. Modifying Avalon Streaming Blocks 4.7.4.3. Restrictions for DSP Builder Designs with Avalon Streaming Interface and AXI4-Stream Blocks 4.7.4.4. Connecting Conduit Interfaces
5. Primitive Library Blocks Tutorial x
5.1. Creating a Fibonacci Design from the DSP Builder Primitive Library 5.2. Setting the Parameters on the Testbench Source Blocks 5.3. Simulating the Fibonacci Design in Simulink 5.4. Modifying the DSP Builder Fibonacci Design to Generate Vector Signals 5.5. Simulating the RTL of the Fibonacci Design
6. IP Tutorial x
6.1. Creating an IP Design 6.2. Simulating the IP Design in Simulink 6.3. Viewing Timing Closure and Viewing Resource Utilization for the DSP Builder IP Design 6.4. Reparameterizing the DSP Builder FIR Filter to Double the Number of Channels 6.5. Doubling the Target Clock Rate for a DSP Builder IP Design
7. DSP Builder for Intel FPGAs (Advanced Blockset) Design Examples and Reference Designs x
7.1. DSP Builder Design Configuration Block Design Examples 7.2. DSP Builder FFT Design Examples 7.3. DSP Builder DDC Design Example 7.4. DSP Builder Filter Design Examples 7.5. DSP Builder Finite State Machine Design Example 7.6. DSP Builder Folding Design Examples 7.7. DSP Builder Floating Point Design Examples 7.8. DSP Builder Flow Control Design Examples 7.9. DSP Builder HDL Import Design Example 7.10. DSP Builder Host Interface Design Examples 7.11. DSP Builder Fixed-Point Matrix Multiply Engine Design Example 7.12. DSP Builder Platform Design Examples 7.13. DSP Builder Primitive Block Design Examples 7.14. DSP Builder Reference Designs 7.15. DSP Builder Waveform Synthesis Design Examples
7.1. DSP Builder Design Configuration Block Design Examples x
7.1.1. Scale 7.1.2. Local Threshold
7.2. DSP Builder FFT Design Examples x
7.2.1. FFT 7.2.2. FFT without BitReverseCoreC Block 7.2.3. IFFT 7.2.4. IFFT without BitReverseCoreC Block 7.2.5. Floating-Point FFT 7.2.6. Floating-Point FFT without BitReverseCoreC Block 7.2.7. Floating-Point iFFT 7.2.8. Floating-Point iFFT without BitReverseCoreC Block 7.2.9. Multichannel FFT 7.2.10. Multiwire Transpose 7.2.11. Parallel FFT 7.2.12. Parallel Floating-Point FFT 7.2.13. Single-Wire Transpose 7.2.14. Switchable FFT/iFFT 7.2.15. Variable-Size Fixed-Point FFT 7.2.16. Variable-Size Fixed-Point FFT without BitReverseCoreC Block 7.2.17. Variable-Size Fixed-Point iFFT 7.2.18. Variable-Size Fixed-Point iFFT without BitReverseCoreC Block 7.2.19. Variable-Size Floating-Point FFT 7.2.20. Variable-Size Floating-Point FFT without BitReverseCoreC Block 7.2.21. Variable-Size Floating-Point iFFT 7.2.22. Variable-Size Floating-Point iFFT without BitReverseCoreC Block 7.2.23. Variable-Size Low-Resource FFT 7.2.24. Variable-Size Low-Resource Real-Time FFT 7.2.25. Variable-Size Supersampled FFT
7.3. DSP Builder DDC Design Example x
7.3.1. DDC Design Example Subsystem 7.3.2. Building the DDC Design Example
7.3.2. Building the DDC Design Example x
7.3.2.1. DDC Design Example Generated Files
7.4. DSP Builder Filter Design Examples x
7.4.1. Complex FIR Filter 7.4.2. Decimating CIC Filter 7.4.3. Decimating FIR Filter 7.4.4. Filter Chain with Forward Flow Control 7.4.5. FIR Filter with Exposed Bus 7.4.6. Fractional FIR Filter Chain 7.4.7. Fractional-Rate FIR Filter 7.4.8. Half-Band FIR Filter 7.4.9. IIR: Full-rate Fixed-point 7.4.10. IIR: Full-rate Floating-point 7.4.11. Interpolating CIC Filter 7.4.12. Interpolating FIR Filter 7.4.13. Interpolating FIR Filter with Multiple Coefficient Banks 7.4.14. Interpolating FIR Filter with Updating Coefficient Banks 7.4.15. Root-Raised Cosine FIR Filter 7.4.16. Single-Rate FIR Filter 7.4.17. Super-Sample Decimating FIR Filter 7.4.18. Super-Sample Fractional FIR Filter 7.4.19. Super-Sample Interpolating FIR Filter 7.4.20. Variable-Rate CIC Filter
7.6. DSP Builder Folding Design Examples x
7.6.1. Position, Speed, and Current Control for AC Motors 7.6.2. Position, Speed, and Current Control for AC Motors (with ALU Folding) 7.6.3. About FOC 7.6.4. Folded FIR Filter
7.7. DSP Builder Floating Point Design Examples x
7.7.1. Black-Scholes Floating Point 7.7.2. Double-Precision Real Floating-Point Matrix Multiply 7.7.3. Fine Doppler Estimator 7.7.4. Floating-Point Mandlebrot Set 7.7.5. General Real Matrix Multiply One Cycle Per Output 7.7.6. Newton Root Finding Tutorial Step 1—Iteration 7.7.7. Newton Root Finding Tutorial Step 2—Convergence 7.7.8. Newton Root Finding Tutorial Step 3—Valid 7.7.9. Newton Root Finding Tutorial Step 4—Control 7.7.10. Newton Root Finding Tutorial Step 5—Final 7.7.11. Normalizer 7.7.12. Single-Precision Complex Floating-Point Matrix Multiply 7.7.13. Single-Precision Real Floating-Point Matrix Multiply 7.7.14. Simple Nonadaptive 2D Beamformer
7.8. DSP Builder Flow Control Design Examples x
7.8.1. Avalon-ST Interface (Input and Output FIFO Buffer) with Backpressure 7.8.2. Avalon-ST Interface (Output FIFO Buffer) with Backpressure 7.8.3. Kronecker Tensor Product 7.8.4. Parallel Loops 7.8.5. Primitive FIR with Back Pressure 7.8.6. Primitive FIR with Forward Pressure 7.8.7. Primitive Systolic FIR with Forward Flow Control 7.8.8. Rectangular Nested Loop 7.8.9. Sequential Loops 7.8.10. Triangular Nested Loop
7.9. DSP Builder HDL Import Design Example x
7.9.1. Performing a Cosimulation
7.10. DSP Builder Host Interface Design Examples x
7.10.1. Memory-Mapped Registers
7.12. DSP Builder Platform Design Examples x
7.12.1. 16-Channel DDC 7.12.2. 16-Channel DUC 7.12.3. 2-Antenna DUC for WiMAX 7.12.4. 2-Channel DUC 7.12.5. Super-Sample Rate Digital Upconverter
7.13. DSP Builder Primitive Block Design Examples x
7.13.1. 8×8 Inverse Discrete Cosine Transform 7.13.2. Automatic Gain Control 7.13.3. Bit Combine for Boolean Vectors 7.13.4. Bit Extract for Boolean Vectors 7.13.5. Color Space Converter 7.13.6. CORDIC from Primitive Blocks 7.13.7. Digital Predistortion Forward Path 7.13.8. Fibonacci Series 7.13.9. Folded Vector Sort 7.13.10. Fractional Square Root Using CORDIC 7.13.11. Fixed-point Maths Functions 7.13.12. Gaussian Random Number Generator 7.13.13. Hello World 7.13.14. Hybrid Direct Form and Transpose Form FIR Filter 7.13.15. Loadable Counter 7.13.16. Matrix Initialization of LUT 7.13.17. Matrix Initialization of Vector Memories 7.13.18. Multichannel IIR Filter 7.13.19. Quadrature Amplitude Modulation 7.13.20. Reinterpret Cast for Bit Packing and Unpacking 7.13.21. Run-time Configurable Decimating and Interpolating Half-Rate FIR Filter 7.13.22. Square Root Using CORDIC 7.13.23. Test CORDIC Functions with the CORDIC Block 7.13.24. Uniform Random Number Generator 7.13.25. Vector Sort—Sequential 7.13.26. Vector Sort—Iterative 7.13.27. Vector Initialization of Sample Delay 7.13.28. Wide Single-Channel Accumulators
7.14. DSP Builder Reference Designs x
7.14.1. 1-Antenna WiMAX DDC 7.14.2. 2-Antenna WiMAX DDC 7.14.3. 1-Antenna WiMAX DUC 7.14.4. 2-Antenna WiMAX DUC 7.14.5. 4-Carrier, 2-Antenna W-CDMA DDC 7.14.6. 1-Carrier, 2-Antenna W-CDMA DDC 7.14.7. 4-Carrier, 2-Antenna W-CDMA DUC 7.14.8. 4-Carrier, 4-Antenna DUC and DDC for LTE 7.14.9. 1-Carrier, 2-Antenna W-CDMA DDC 7.14.10. 4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 32 7.14.11. 4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 48 7.14.12. 4-Carrier, 2-Antenna High-Speed W-CDMA DUC at 307.2 MHz with Total Rate Change 40 7.14.13. Cholesky-based Matrix Inversion 7.14.14. Cholesky Solver Multiple Channels 7.14.15. Crest Factor Reduction 7.14.16. Direct RF with Synthesizable Testbench 7.14.17. Dynamic Decimating FIR Filter 7.14.18. Multichannel QR Decompostion 7.14.19. QR Decompostion 7.14.20. QRD Solver 7.14.21. Reconfigurable Decimation Filter 7.14.22. Single-Channel 10-MHz LTE Transmitter 7.14.23. STAP Radar Forward and Backward Substitution 7.14.24. STAP Radar Steering Generation 7.14.25. STAP Radar QR Decomposition 192x204 7.14.26. Time Delay Beamformer 7.14.27. Transmit and Receive Modem 7.14.28. Variable Integer Rate Decimation Filter
7.15. DSP Builder Waveform Synthesis Design Examples x
7.15.1. Complex Mixer 7.15.2. Four Channel, Two Banks NCO 7.15.3. Four Channel, Four Banks NCO 7.15.4. Four Channel, Eight Banks, Two Wires NCO 7.15.5. Four Channel, 16 Banks NCO 7.15.6. IP 7.15.7. NCO 7.15.8. NCO with Exposed Bus 7.15.9. Real Mixer 7.15.10. Super-sample NCO
8. DSP Builder Design Rules, Design Recommendations, and Troubleshooting x
8.1. DSP Builder Design Rules and Recommendations 8.2. Troubleshooting DSP Builder Designs
8.2. Troubleshooting DSP Builder Designs x
8.2.1. About Loops 8.2.2. Closing Timed feedback Loops 8.2.3. Loops, Clock Cycles, and Data Cycles
9. About DSP Builder for Intel FPGAs Optimization x
9.1. Associating DSP Builder with MATLAB 9.2. Setting Up Simulink for DSP Builder Designs 9.3. The DSP Builder Windows Shortcut 9.4. Setting DSP Builder Design Parameters with MATLAB Scripts 9.5. Managing your Designs 9.6. How to Manage Latency 9.7. Flow Control in DSP Builder Designs 9.8. Reset Minimization 9.9. About Importing HDL
9.2. Setting Up Simulink for DSP Builder Designs x
9.2.1. Setting Up Simulink Solver 9.2.2. Setting Up Simulink Signal Display Option
9.4. Setting DSP Builder Design Parameters with MATLAB Scripts x
9.4.1. Running Setup Scripts Automatically 9.4.2. Defining Unique DSP Builder Design Parameters 9.4.3. Example DSP Builder Custom Scripts
9.5. Managing your Designs x
9.5.1. Managing Basic Parameters 9.5.2. Creating User Libraries and Converting a Primitive Subsystem into a Custom Block 9.5.3. Revision Control
9.6. How to Manage Latency x
9.6.1. Reading the Added Latency Value for an IP Block 9.6.2. Zero Latency Example 9.6.3. Implicit Delays in DSP Builder Designs 9.6.4. Distributed Delays in DSP Builder Designs 9.6.5. Latency and fMAX Constraint Conflicts in DSP Builder Designs 9.6.6. Control Units Delays
10. About Folding x
10.1. ALU Folding 10.2. Removing Resource Sharing Folding
10.1. ALU Folding x
10.1.1. ALU Folding Limitations 10.1.2. ALU Folding Parameters 10.1.3. ALU Folding Simulation Rate 10.1.4. Using ALU Folding 10.1.5. Using Automated Verification 10.1.6. Ready Signal 10.1.7. Connecting the ALU Folding Ready Signal 10.1.8. About the ALU Folding Start of Packet Signal
11. Floating-Point Data Types x
11.1. DSP Builder Floating-Point Data Type Features 11.2. DSP Builder Supported Floating-Point Data Types 11.3. DSP Builder Round-Off Errors 11.4. Trading Off Logic Utilization and Accuracy in DSP Builder Designs 11.5. Upgrading Pre v14.0 Designs 11.6. Floating-Point Sine Wave Generator Tutorial 11.7. Newton-Raphson Root Finding Tutorial 11.8. Forcing Soft Floating-point Data Types with the Advanced Options
11.6. Floating-Point Sine Wave Generator Tutorial x
11.6.1. Creating a Sine Wave Generator in DSP Builder 11.6.2. Using Data Type Variables to Parameterize Designs 11.6.3. Using Data-Type Propagation in DSP Builder Designs 11.6.4. DSP Builder Testbench Verification
11.6.4. DSP Builder Testbench Verification x
11.6.4.1. Tuning ATB Thresholds 11.6.4.2. Writing Application Specific Verification 11.6.4.3. Performing Bit-Accurate Simulation 11.6.4.4. Adder Trees and Scalar Products 11.6.4.5. Creating Floating-Point Accumulators for Designs that Use Iteration
11.7. Newton-Raphson Root Finding Tutorial x
11.7.1. Implementing the Newton Design 11.7.2. Improving DSP Builder Floating-Point Designs
12. Design Configuration Library x
12.1. Avalon Memory-Mapped Agent Settings (AvalonMemoryMappedAgentSettings) 12.2. Control 12.3. Device 12.4. LocalThreshold
12.2. Control x
12.2.1. DSP Builder Memory and Multiplier Trade-Off Options
13. IP Library x
13.1. Channel Filter and Waveform Library 13.2. Dependent Delay Library 13.3. FFT IP Library
13.1. Channel Filter and Waveform Library x
13.1.1. DSP Builder FIR and CIC Filters 13.1.2. DSP Builder FIR Filters 13.1.3. Channel Viewer (ChanView) 13.1.4. Complex Mixer (ComplexMixer) 13.1.5. Decimating CIC 13.1.6. Decimating FIR 13.1.7. Fractional Rate FIR 13.1.8. Interpolating CIC 13.1.9. Interpolating FIR 13.1.10. NCO 13.1.11. Real Mixer (Mixer) 13.1.12. Scale 13.1.13. Single-Rate FIR
13.1.1. DSP Builder FIR and CIC Filters x
13.1.1.1. Common CIC and FIR Filter Features 13.1.1.2. Updated Help 13.1.1.3. Half-Band and L-Band Nyquist FIR Filters 13.1.1.4. Parameterization of CIC and FIR Filters 13.1.1.5. Setting and Changing FIR Filter Coefficients at Runtime in DSP Builder
13.1.2. DSP Builder FIR Filters x
13.1.2.1. FIR Filter Avalon-MM Interfaces 13.1.2.2. Reconfigurable FIR Filters
13.1.10. NCO x
13.1.10.1. NCO Block Phase Increment and Inversion 13.1.10.2. NCO Block Phase Increment Memory Registers 13.1.10.3. NCO Block Frequency Hopping
13.3. FFT IP Library x
13.3.1. Bit Reverse Core C (BitReverseCoreC and VariableBitReverse) 13.3.2. FFT (FFT, FFT_Light, VFFT, VFFT_Light)
14. Interfaces Library x
14.1. Memory-Mapped Library 14.2. Streaming Library
14.1. Memory-Mapped Library x
14.1.1. Bus Slave (BusSlave) 14.1.2. Bus Stimulus (BusStimulus) 14.1.3. Bus Stimulus File Reader (Bus StimulusFileReader) 14.1.4. External Memory, Memory Read, Memory Write Memory Read Block Memory Write Block 14.1.5. Register Bit (RegBit) 14.1.6. Register Field (RegField) 14.1.7. Register Out (RegOut) 14.1.8. Shared Memory (SharedMem)
14.2. Streaming Library x
14.2.1. Avalon-ST Input (AStInput) 14.2.2. Avalon-ST Input FIFO Buffer (AStInputFIFO) 14.2.3. Avalon-ST Output (AStOutput) 14.2.4. AXI4-Stream Blocks (AXI4StreamReceiver and AXI4StreamTransmitter)
15. Primitives Library x
15.1. Vector and Complex Type Support 15.2. DFT Design Elements Library 15.3. FFT Design Elements Library 15.4. Primitive Basic Blocks Library 15.5. Primitive Configuration Library 15.6. Primitive Design Elements Library
15.1. Vector and Complex Type Support x
15.1.1. Vector Type Support 15.1.2. Complex Support
15.1.1. Vector Type Support x
15.1.1.1. Element by Element Mode 15.1.1.2. Mathematical Vector Mode 15.1.1.3. Interactions with Simulink
15.1.2. Complex Support x
15.1.2.1. Interactions with Simulink
15.2. DFT Design Elements Library x
15.2.1. DFT (DFT) 15.2.2. Reorder (ReorderBlock) 15.2.3. Reorder and Rescale (ReorderAndRescale)
15.3. FFT Design Elements Library x
15.3.1. About Pruning and Twiddle for FFT Blocks 15.3.2. Bit Vector Combine (BitVectorCombine) 15.3.3. Butterfly Unit (BFU) 15.3.4. Butterfly I C (BFIC) (Deprecated) 15.3.5. Butterfly II C (BFIIC) (Deprecated) 15.3.6. Choose Bits (ChooseBits) 15.3.7. Crossover Switch (XSwitch) 15.3.8. Dual Twiddle Memory (DualTwiddleMemoryC) 15.3.9. Edge Detect (EdgeDetect) 15.3.10. Floating-Point Twiddle Generator (TwiddleGenF) (Deprecated) 15.3.11. Fully-Parallel FFTs (FFT2P, FFT4P, FFT8P, FFT16P, FFT32P, and FFT64P) 15.3.12. Fully-Parallel FFTs with Flexible Ordering (FFT2X, FFT4X, FFT8X, FFT16X, FFT32X, and FFT64X) 15.3.13. General Multitwiddle and General Twiddle (GeneralMultiTwiddle, GeneralMultVTwiddle, GeneralTwiddle, GeneralVTwiddle) 15.3.14. Hybrid FFT (Hybrid_FFT, HybridVFFT, HybridVFFT_btb) 15.3.15. Multiwire Transpose (MultiwireTranspose) 15.3.16. Parallel Pipelined FFT (PFFT_Pipe) 15.3.17. Pulse Divider (PulseDivider) 15.3.18. Pulse Multiplier (PulseMultiplier) 15.3.19. Single-Wire Transpose (Transpose) 15.3.20. Split Scalar (SplitScalar) 15.3.21. Streaming FFTs (FFT2, FFT4, VFFT2, and VFFT4) 15.3.22. Stretch Pulse (StretchPulse) 15.3.23. Twiddle Angle (TwiddleAngle) 15.3.24. Twiddle Generator (TwiddleGenC) Deprecated 15.3.25. Twiddle and Variable Twiddle (Twiddle and VTwiddle) 15.3.26. Twiddle ROM (TwiddleRom, TwiddleMultRom and TwiddleRomF (deprecated))
15.4. Primitive Basic Blocks Library x
15.4.1. Absolute Value (Abs) 15.4.2. Accumulator (Acc) 15.4.3. Add 15.4.4. Add SLoad (AddSLoad) 15.4.5. AddSub 15.4.6. AddSubFused 15.4.7. AND Gate (And) 15.4.8. Bit Combine (BitCombine) 15.4.9. Bit Extract (BitExtract) 15.4.10. Bit Reverse (BitReverse) 15.4.11. Compare (CmpCtrl) 15.4.12. Complex Conjugate (ComplexConjugate) 15.4.13. Compare Equality (CmpEQ) 15.4.14. Compare Greater Than (CmpGE) 15.4.15. Compare Less Than (CmpLT) 15.4.16. Compare Not Equal (CmpNE) 15.4.17. Constant (Const) 15.4.18. Constant Multiply (Const Mult) 15.4.19. Convert 15.4.20. CORDIC 15.4.21. Counter 15.4.22. Count Leading Zeros, Ones, or Sign Bits (CLZ) 15.4.23. Dual Memory (DualMem) 15.4.24. Demultiplexer (Demux) 15.4.25. Divide 15.4.26. Fanout 15.4.27. FIFO 15.4.28. Floating-point Classifier (FloatClass) 15.4.29. Floating-point Multiply Accumulate (MultAcc) 15.4.30. ForLoop 15.4.31. Load Exponent (LdExp) 15.4.32. Left Shift (LShift) 15.4.33. Loadable Counter (LoadableCounter) 15.4.34. Look-Up Table (Lut) 15.4.35. Loop 15.4.36. Math 15.4.37. Minimum and Maximum (MinMax) 15.4.38. MinMaxCtrl 15.4.39. Multiply (Mult) 15.4.40. Multiplexer (Mux) 15.4.41. NAND Gate (Nand) 15.4.42. Negate 15.4.43. NOR Gate (Nor) 15.4.44. NOT Gate (Not) 15.4.45. OR Gate (Or) 15.4.46. Polynomial 15.4.47. Ready 15.4.48. Reinterpret Cast (ReinterpretCast) 15.4.49. Round 15.4.50. Sample Delay (SampleDelay) 15.4.51. Scalar Product 15.4.52. Select 15.4.53. Sequence 15.4.54. Shift 15.4.55. Sqrt 15.4.56. Subtract (Sub) 15.4.57. Sum of Elements (SumOfElements) 15.4.58. Trig 15.4.59. XNOR Gate (Xnor) 15.4.60. XOR Gate (Xor)
15.5. Primitive Configuration Library x
15.5.1. Channel In (ChannelIn) 15.5.2. Channel Out (ChannelOut) 15.5.3. General Purpose Input (GPIn) 15.5.4. General Purpose Output (GPOut) 15.5.5. Synthesis Information (SynthesisInfo)
15.5.5. Synthesis Information (SynthesisInfo) x
15.5.5.1. Scheduled Synthesis 15.5.5.2. Updated Help
15.6. Primitive Design Elements Library x
15.6.1. Anchored Delay 15.6.2. Complex to Real-Imag 15.6.3. Enabled Delay Line 15.6.4. Enabled Feedback Delay 15.6.5. Expand Scalar (ExpandScalar) 15.6.6. Finite State Machine 15.6.7. Nested Loops (NestedLoop1, NestedLoop2, NestedLoop3) 15.6.8. Pause 15.6.9. Reset-Priority Latch (SRlatch_PS) 15.6.10. Same Data Type (SameDT) 15.6.11. Set-Priority Latch (SRlatch) 15.6.12. Single-Cycle Latency Latch (latch_1L) 15.6.13. Tapped Line Delay (TappedLineDelay) 15.6.14. Variable Super-Sample Delay (VariableDelay) 15.6.15. Vector Fanout (VectorFanout) 15.6.16. Vector Multiplexer (VectorMux) 15.6.17. Zero-Latency Latch (latch_0L)
16. Utilities Library x
16.1. Analyze and Test Library 16.2. HDL Import Library
16.1. Analyze and Test Library x
16.1.1. Capture Values 16.1.2. Dechannelizer 16.1.3. Channelizer 16.1.4. Display Resources 16.1.5. Edit Params 16.1.6. Pause
16.2. HDL Import Library x
16.2.1. HDL Import 16.2.2. HDL Import Config
1. Answers to Top FAQs
2. About DSP Builder for Intel® FPGAs
3. DSP Builder for Intel FPGAs Advanced Blockset Getting Started
4. DSP Builder Design Flow
5. Primitive Library Blocks Tutorial
6. IP Tutorial
7. DSP Builder for Intel FPGAs (Advanced Blockset) Design Examples and Reference Designs
8. DSP Builder Design Rules, Design Recommendations, and Troubleshooting
9. About DSP Builder for Intel FPGAs Optimization
10. About Folding
11. Floating-Point Data Types
12. Design Configuration Library
13. IP Library
14. Interfaces Library
15. Primitives Library
16. Utilities Library
17. Simulink Supported Blocks
18. Document Revision History for DSP Builder for Intel FPGAs (Advanced Blockset) Handbook

14.1.4. External Memory, Memory Read, Memory Write

The DSP Builder External Memory block specifies characteristics of external memory and related Avalon-MM interfaces. DSP Builder uses this information to set bit widths on related interface ports in simulation, generated HDL and to build an external memory simulation model. The Memory Read and Memory Write blocks provide (read or write) access to associated external memory models in simulation. In HDL, each of these blocks is driving dedicated Avalon memory-mapped host interface. Associate read and write ports with External Memory blocks using identifiers. Connect these interfaces to a DDR3 SDRAM controller in your system-level design in Platform Designer.

Always add the External Memory block to the top-level of your DSP Builder design (similar to Control or Signals blocks).

Your design can have several instances of these blocks, but you must give them separate identifiers. DSP Builder creates a separate simulation model for each of these blocks.

Table 71.  External Memory Block Parameters
Parameter Values Description
Identifier Numeric value A unique identifier for External Memory block that you should set on Memory Read or Memory Write block to associate these blocks with the External Memory block.
Avalon-MM Interface Data Width

A valid Avalon-MM interface data width value.

Should be power of 2.

The width of the data signal in the generated Avalon memory-mapped host interfaces for associated Memory Read and Memory Write blocks.

Set the data ports on these blocks to the same width.

Memory Data Width

Should be less than or equal to Avalon-MM Interface Data Width.

The ratio between these two widths should be a power of 2.

The data width of the actual external memory.

Only use to calculate the size of the memory which affects the width of address bus.

Set this parameter to a quarter of the Avalon MM Interface Data Width parameter to define DDR memory operating at half rate.

Number of Rows

Numeric value.

Should be power of 2.

The number of rows, columns, and banks of the actual physical memory that you connect to the DSP Builder design.

Carefully chose access patterns based on these values to get the best performance of external memory.

Number of Columns
Number of Banks
Memory Size Read-Only parameter

This parameter displays the size of the external memory based on the specified number of rows, columns, banks and memory data width.

DSP Builder uses the following equation:

memory_size = rows * columns * banks * memory_data_width

The width of the address bus on Avalon memory-mapped host interfaces generated for associated Memory Read and Memory Write blocks, and the width of address input on these blocks, is:

address_width = log2(memory_size)

Table 72.  Parameters that Only Affect Simulation
Parameter Values Description
Signal Busy for Specified Amount of Simulation Time (%)

off

12.5, 25, 50, 75, 87.5

Any value other than off forces external memory simulation model into a busy state (the model refuses read or write requests) at random points during simulation.

The actual value limits the overall busy time compared to design simulation time.

The busy state of the memory model is indicated with low value on ready ports for associated Memory Read or Memory Write blocks.

If this feature is enabled, you may need to increase overall simulation time in order to get all requests to external memory through. Longer simulation time will be required for higher limits.

Show Diagnostic ports Boolean switch Turn on this option to add diagnostic ports, to External Memory blocks, which display the state of the simulation model.
Dump Memory Region into File Boolean switch

Turn on so the External Memory block dumps its content for the specified region into a file.

Each Avalon MM Interface Data Width value occupies a line in the file and is printed as a sequence of 8-bit decimal values.

For External Memory blocks with Avalon MM Interface Data Width set to 16, the lines in the dump file have the following format

a[7:0] a1[15:8]

Dump File Name Valid file name

The name of the dump file with extension (DSP Builder does not add an extension)

The dump file is created in the current directory.

Dump Region Start Address Valid word address The start address of the region in external memory that should be dumped.
Dump Region Size Non negative number The number of words that should be dumped starting with the specified address.
Memory Initialization Start Address A valid word address —
Memory Initialization Data A 1-D or 2-D matrix

DSP Builder writes this data to the memory from the Start Address. DSP Builder does not convert the data type. You must use the data type you want. The type must be:

  • single
  • double
  • INT8
  • UINT8
  • INT16
  • UINT16
  • INT32
  • UINT32
  • INT64
  • UINT64

Where the Avalon-MM interface data width is wider than the data type, DSP Builder packs the initialization data into the words first, before moving on to the next address. You can use a 2-D matrix, where each column represents an address in the memory and each row represents a bit-slice in the word.

Table 73.  External Memory Block Diagnostic PortsYou can enable these ports through dedicated parameters.
Name Direction Type Description
reading Output Boolean High when external memory model is performing reading operation; otherwise low.
writing Output Boolean High when external memory model is performing writing operation; otherwise low.
busy Output Boolean High when external memory model is in busy state; otherwise low.

Memory Read Block

This block is an access point for reading from the associated External Memory block. It provides a simple interface with ready and valid based handshaking for reading. In generated HDL, use this block as an adapter between the provided interface and the Avalon memory-mapped host interface. You can place these blocks at any level of hierarchy under the DSP Builder device level block. The design can contain several of these blocks, with each of the blocks accessing the associated External Memory block.

Table 74.  Memory Read Parameters
Parameter Values Description
Identifier One of identifiers set for External Memory blocks in the design Set to match an identifier on one of the External Memory blocks in the design.
Maximum Burst Size

off

2, 4, 8, 16, 32, 64, 128, 256, 512, 1024

If the value is set to off, DSP Builder does not allow burst requests.

For other values, DSP Builder adds a new port to specify an actual size (less than or equal specified Maximum Burst Size) for each burst request.

Table 75.  Memory Read Ports
Name Direction Type Description
read Input Boolean Set this port to high to indicate a new read request.
address Input Unsigned Integer

Sets the address for the request.

The width of this port is: log2(memory_size), memory_size is the size of associated External Memory.

burstcount Input Unsigned Integer

Optional. DSP Builder adds if Maximum Burst Count is not off.

Sets the actual number of bursts for the read request.

If you initiate a burst request, update this port and the read and address ports once at the beginning of request.

The width of this port is:

log2(max_burst_count) + 1

valid Output Boolean Indicates that the valid response is available on the data port.
ready Output Boolean

Indicates that the block (associated memory) is ready to accept new request.

Do not update input ports if this value is low.

data Output Unsigned Integer

Contains the read data.

The width of this port is based on the Avalon MM Interface Data Width parameter of the associated External Memory.

Memory Write Block

This block is an access point for writing to the associated external memory model. It provides a simple interface with ready and valid based handshaking for writing. In generated HDL, this block is an adapter between the provided interface and the actual Avalon memory-mapped host interface. Place these blocks at any level of hierarchy under DSP Builder device level block. The design can contain several of these blocks, with each of the blocks accessing the associated External Memory block.

Table 76.  Memory Write Parameters
Parameter Values Description
Identifier One of identifiers set for External Memory blocks in the design Set to match an identifier on one of the External Memory blocks in the design.
Byte Enables Boolean width

Activate this parameter to use byte enables for the write request.

If enabled, DSP Builder adds a separate port to provide byte enable values.

Maximum Burst Size

off

2, 4, 8, 16, 32, 64, 128, 256, 512, 1024

If the value is set to off, DSP Builder does not allow burst requests.

For any other values, DSP Builder adds a new port to specify an actual size (less than or equal specified Maximum Burst Size) for each burst request.

If you initiate a burst write, External Memory blocks ignore subsequent addresses until the burst is completed.

When a burst write is in progress, DSP Builder queues the read and write requests from associated Memory Read and Memory Write blocks until the write burst is completed.

Table 77.  Memory Write Ports
Name Direction Type Description
write Input Boolean Set this port to high to indicate new write request to associated External Memory blocks.
address Input Unsigned integer

Sets the address for write request.

The width of this port is the Avalon MM Interface Data Width parameter value on the associated External Memory block.

data Input Unsigned integer

Sets the write data.

The width of this port is: log2(memory_size), memory_size is the size of associated External Memory.

byteenable Input Unsigned integer

Optional. DSP Builder adds byteenable when the Byte Enables parameter is on.

Sets the byte enables for write data.

The width of this port is:

data_port_width / 8

burstcount Input Unsigned integer

Optional. DSP Builder adds burstcount when the Maximum Burst Count parameter is not off.

Sets the actual burst count for burst write requests.

When you initiate a burst request, ensure you update the address port and this port once at the beginning of request. Update the write port every time you update the data port to supply the next portion of burst data. For example, if you provide a new portion of data every cycle, keep the write port high throughout the burst.

The width of this port is set as:

log2(mac_burst_count)+1

ready Output Boolean

Indicates whether the block is ready to accept a new write request or a continuation of ongoing burst request.

Do not update input ports if this output is low.

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