External Memory Interfaces Intel Agilex® 7 F-Series and I-Series FPGA IP Core Release Notes

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Date 7/19/2023
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1. External Memory Interfaces Intel Agilex 7 F-Series and I-Series FPGA IP Core Release Notes
1. External Memory Interfaces Intel Agilex 7 F-Series and I-Series FPGA IP Core Release Notes x
1.1. External Memory Interfaces Intel Agilex® 7 F-Series and I-Series FPGA IP v2.7.1 1.2. External Memory Interfaces Intel Agilex® 7 F-Series and I-Series FPGA IP v2.7.0 1.3. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.6.1 1.4. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.6.1 1.5. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.6.0 1.6. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.5.0 1.7. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.4.2 1.8. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.4.0 1.9. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.3.0 1.10. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.3.0 1.11. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.2.0 1.12. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.1.0 1.13. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.0.0
1. External Memory Interfaces Intel Agilex 7 F-Series and I-Series FPGA IP Core Release Notes

1.13. External Memory Interfaces Intel Agilex® 7 FPGA IP v2.0.0

Table 68.  v2.0.0 2019.12.16
Description Impact
Verified in the Intel® Quartus® Prime software v19.4. Provides external memory interface IP for DDR4 external memory for Intel Agilex® 7 devices. The tables that follow summarize speed and feature support.
Table 69.  Agilex Fabric EMIF IP Speed Support Summary
      Max Rate (Mbps/MHz)   -1 -2 -3
Protocol Category Subcategory -1 -2 -3 Support Detail S C T H S C T H S C T H
DDR4 Memory Format UDIMM 3200/1600 (1DPC 1R) 2666/1333 (1DPC 1R) 2400/1200 (1DPC 1R)   X X X up to 1200 MHz X X X X
2666/1333 (1DPC 2R) 2400/1200 (1DPC 2R) 2133/1067 (1DPC 2R)   X X X   X X X  
2666/1333 (2DPC 1R) 2400/1200 (2DPC 1R) 2133/1067 (2DPC 1R)                  
2133/1067 (2DPC 2R) 1866/933 (2DPC 2R) 1600/800 (2DPC 2R)                  
RDIMM 3200/1600 (1DPC 1R) 2666/1333 (1DPC 1R) 2400/1200 (1DPC 1R) non-3DS X X X up to 1200 MHz X X X X
2666/1333 (1DPC 2R) 2400/1200 (1DPC 2R) 2133/1067 (1DPC 2R) non-3DS X X X   X X X  
2666/1333 (2DPC 1R) 2400/1200 (2DPC 1R) 2133/1067 (2DPC 1R) non-3DS X X X   X X X  
2133/1067 (2DPC 2R) 1866/933 (2DPC 2R) 1600/800 (2DPC 2R) non-3DS (x8 & x4 RDIMM)              
2666/1333 (1DPC 2R) 2400/1200 (1DPC 2R) 3DS 2S2R(2H) & 2D4R(4H) 3DS 2S2R(2H) & 2D4R(4H)
2133/1067 (2DPC 2R) 1866/933 (2DPC 2R) 3DS 2S2R(2H) & 2D4R(4H) 3DS 2S2R(2H) & 2D4R(4H)
Component 3200/1600 (1R) 2666/1333 (1R) 2400/1200 (1R) x8,x16, 3DS, 1R clamshell, 1R twin-die x16 X X X up to 1200 MHz X X X X
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R) x8, x16                
2666/1333 (2R) 2666/1333 (2R) 2400/1200 (2R) clamshell 2R              
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
Table 70.  Agilex HPS EMIF IP Speed Support Summary
      Max Rate (Mbps/MHz)   -1 -2 -3
Protocol Category Subcategory -1 -2 -3 Support Detail S C T H S C T H S C T H
DDR4 Memory Format UDIMM 3200/1600 (1DPC 1R) 2666/1333 (1DPC 1R) 2400/1200 (1DPC 1R)   X X X up to 1200 MHz X X X X
SODIMM 3200/1600 (1DPC 1R) 2666/1333 (1DPC 1R) 2400/1200 (1DPC 1R)   X X X X X X X X
RDIMM 3200/1600 (1DPC 1R) 2666/1333 (1DPC 1R) 2400/1200 (1DPC 1R) non-3DS X X X up to 1200 MHz X X X X
2666/1333 (1DPC 2R) 2400/1200 (1DPC 2R) 2133/1067 (1DPC 2R) non-3DS X X X   X X X  
Component 3200/1600 (1DPC 1R) 2666/1333 (1DPC 1R) 2400/1200 (1DPC 1R) x8,x16,3DS, single-rank clamshell, single-rank twin-die x16 X X X up to 1200 MHz X X X X
2666/1333 (1DPC 2R) 2666/1333 (1DPC 2R) 2400/1200 (1DPC 2R) x8, x16,                
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
Table 71.  Agilex EMIF IP Feature Support Summary
         
Protocol Category Subcategory Supported? S C T H
DDR4 Interface Width <=72 with DIMM X X X X X
<= 72 Component X X X X X
Controller Hard Controller X X X X X
PHY Hard PHY X X X X X
3DS 3DS X (1D2R only) X X X  
Design example X X X X X
Rate (core) Quarter Rate X X X X X
DBI Read DBI X X X X X
Write DBI X X X X X
Mirroring Address mirroring for odd ranks for multi ranks DIMM X X X X X
DM DM Pins X X X X X
Preamble Read Preamble Settings X X X X X
Write Preamble Settings X X X X X
Refresh 1 Temperature Controlled Refresh
Fine Granularity Refresh
Auto Self-refresh Method
Self-refresh
ODT 1 Input Buffer During Power-down Mode
Controller ECC (soft implementation only) X X X X X
Reordering X X X X X
Auto Power-down X X X X
User Refresh
Auto Precharge X X X
Command Priority
Calibration Address/Command Calibration X X X X X
Multi-rank Calibration X X X X X
Debug EMIF Toolkit X X X X
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = Not validated in hardware.
  • An empty table cell indicates that the feature is not currently supported.
Table 72.  Agilex EMIF HPS IP Feature Support Summary
         
Protocol Category Subcategory Supported? S C T H
DDR4 Interface Width <=72 with DIMM X   X X X
<= 72 Component X   X X X
Controller Hard Controller X   X X X
PHY Hard PHY X   X X X
Rate (core) Quarter Rate X   X X X
DM DM Pins 1 X   X X X
Preamble Read Preamble Settings X   X X X
Write Preamble Settings X   X X X
Refresh 2 Temperature Controlled Refresh
Fine Granularity Refresh
Auto Self-refresh Method
Self-refresh About
ODT 2 Input Buffer During Power-down Mode
Controller ECC        
Reordering X   X X X
Auto Power-down X   X X
Calibration Address/Command Calibration X   X X X
Debug EMIF Toolkit
Support level key:
  • S = simulation support
  • C = compilation support
  • T = timing support
  • H = hardware support

  • X = supported feature.
  • 1 = HPS EMIF always requires DM pins.
  • 2 = Not validated in hardware.
  • An empty table cell indicates that the feature is not currently supported.
Table 73.  Agilex EMIF IP Debug Support Summary
Category Subcategory Supported?
Debug Support On-chip Debug On-chip Debug with Soft Nios®
EMIF Toolkit Calibration Margin X
Rerun Calibration X
Vref Margining
Driver Margining X
Efficiency Monitor
ODT Calibration X
Multi-interface Support X
  • X = supported feature.
  • An empty table cell indicates that the feature is not currently supported.
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