1.1. External Memory Interfaces Intel Agilex® 7 F-Series and I-Series FPGA IP v2.7.1
Description | Impact |
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Verified in the Intel® Quartus® Prime software v23.2. | Provides external memory interface IP for DDR4 and QDR-IV external memory for Intel Agilex® 7 F-Series and I-Series devices. |
Max Rate (Mbps/MHz) | -1 | -2 | -3 | |||||||||||||||
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Protocol | Category | Subcategory | -1 | -2 | -3 | Support Detail | S | C | T | H | S | C | T | H | S | C | T | H |
DDR4 | Memory Format * | UDIMM | 3200/1600 (1DPC 1R) | 2666/1333 (1DPC 1R) | 2400/1200 (1DPC 1R) | X | X | X | X | X | X | X | X | X | X | X | X | |
2666/1333 (1DPC 2R) | 2400/1200 (1DPC 2R) | 2133/1067 (1DPC 2R) | X | X | X | 1 | X | X | X | 1 | X | X | X | 1 | ||||
2666/1333 (2DPC 1R) | 2400/1200 (2DPC 1R) | 2133/1067 (2DPC 1R) | X | X | X | 1 | X | X | X | 1 | X | X | X | 1 | ||||
2133/1067 (2DPC 2R) | 1866/933 (2DPC 2R) | 1600/800 (2DPC 2R) | X | X | X | 1 | X | X | X | 1 | X | X | X | 1 | ||||
RDIMM | 3200/1600 (1DPC 1R) | 2666/1333 (1DPC 1R) | 2400/1200 (1DPC 1R) | non-3DS | X | X | X | X | X | X | X | X | X | X | X | X | ||
2666/1333 (1DPC 2R) | 2400/1200 (1DPC 2R) | 2133/1067 (1DPC 2R) | non-3DS | X | X | X | X | X | X | X | X | X | X | X | X | |||
2666/1333 (2DPC 1R) | 2400/1200 (2DPC 1R) | 2133/1067 (2DPC 1R) | non-3DS | X | X | X | X | X | X | X | X | X | X | X | X | |||
2133/1067 (2DPC 2R) | 1866/933 (2DPC 2R) | 1600/800 (2DPC 2R) | non-3DS | X | X | X | X | X | X | X | X | X | X | X | X | |||
2666/1333 (1DPC 2R) | 2400/1200 (1DPC 2R) | 2133/1067 (1DPC 2R) | 3DS 2S2R(2H) and 2S4R(4H) | X | X | X | X | X | X | X | X | X | X | X | X | |||
2133/1067 (2DPC 2R) | 1866/933 (2DPC 2R) | 1600/800 (2DPC 2R) | 3DS 2S2R(2H) and 2S4R(4H) | X | X | X | X | X | X | X | X | X | X | X | X | |||
Component | 3200/1600 (1R) | 2666/1333 (1R) | 2400/1200 (1R) | x8, x16, x16 Twin-die | X | X | X | X | X | X | X | X | X | X | X | X | ||
2666/1333 (2R) | 2400/1200 (2R) | 2133/1067 (2R) | x8, x8 DDP, x16 | X | X | X | X | X | X | X | X | X | X | X | X | |||
3200/1600 (1R) | 2666/1333 (1R) | 2400/1200 (1R) | Clamshell 1Rx16 | X | X | X | X | X | X | X | X | X | X | X | X | |||
2666/1333 (2R) | 2400/1200 (2R) | 2133/1067 (2R) | Clamshell 2Rx16 | X | X | X | X | X | X | X | X | X | X | X | X | |||
LRDIMM | 2666/1333 (1DPC 2R) | 2666/1333 (1DPC 2R) | 2400/1200 (1DPC 2R) | 1D2R -non 3DS | X | X | X | X | X | X | X | X | X | X | X | X | ||
2666/1333 (1DPC 2R) | 2666/1333 (1DPC 2R) | 2400/1200 (1DPC 2R) | 3DS 2S2R(2H) and 2S4R(4H) | X | X | X | X | X | X | X | X | X | X | X | X | |||
2133/1067 (1DPC 4R) | 2133/1067 (1DPC 4R) | 2133/1067 (1DPC 4R) | non-3DS | X | X | X | X | X | X | X | X | X | X | X | X | |||
2133/1067 (2DPC 2R) | 1866/933 (2DPC 2R) | 1600/800 (2DPC 2R) | 3DS 2S2R(2H) and 2S4R(4H) | X | X | X | X | X | X | X | X | X | X | X | X | |||
SODIMM | 3200/1600 (1DPC 1R) | 2666/1333 (1DPC 1R) | 2400/1200 (1DPC 1R) | x8, x16 | X | X | X | X | X | X | X | X | X | X | X | X | ||
2666/1333 (1DPC 2R) | 2400/1200 (1DPC 2R) | 2133/1067 (1DPC 2R) | x8 only | X | X | X | X | X | X | X | X | X | X | X | X | |||
2666/1333 (2DPC 1R) | 2400/1200 (2DPC 1R) | 2133/1067 (2DPC 1R) | x8, x16 | X | X | X | 7 | X | X | X | 7 | X | X | X | 2 | |||
2133/1067 (2DPC 2R) | 1866/933 (2DPC 2R) | 1600/800 (2DPC 2R) | x8 only | X | X | X | 7 | X | X | X | 7 | X | X | X | 2 | |||
QDR-IV | Memory Protocol | Component - x18 | 2133/1066 | 2133/1066 | 1866/933 | X | X | X | X | X | X | X | X | X | X | X | X | |
Component - x36 | 2133/1066 | 2133/1066 | 1866/933 | X | X | X | X | X | X | X | X | X | X | X | X | |||
Support level key:
Note: Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at www.intc.com.
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Max Rate (Mbps/MHz) | -1 | -2 | -3 | |||||||||||||||
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Protocol | Category | Subcategory | -1 | -2 | -3 | Support Detail | S | C | T | H | S | C | T | H | S | C | T | H |
DDR4 | Memory Format | UDIMM | 3200/1600 (1DPC 1R) | 2666/1333 (1DPC 1R) | 2400/1200 (1DPC 1R) | X | X | X | X | X | X | |||||||
SODIMM | 3200/1600 (1DPC 1R) | 2666/1333 (1DPC 1R) | 2400/1200 (1DPC 1R) | X | X | X | X | X | X | |||||||||
RDIMM | 3200/1600 (1DPC 1R) | 2666/1333 (1DPC 1R) | 2400/1200 (1DPC 1R) | non-3DS | X | X | X | X | X | X | ||||||||
2666/1333 (1DPC 2R) | 2400/1200 (1DPC 2R) | 2133/1067 (1DPC 2R) | non-3DS | X | X | 1 | X | X | 1 | |||||||||
Component | 3200/1600 (1DPC 1R) | 2666/1333 (1DPC 1R) | 2400/1200 (1DPC 1R) | x8,x16,3DS, Single rank clamshell, Single rank twin-die x16 | X | X | X | X | X | X | ||||||||
2666/1333 (1DPC 2R) | 2400/1200 (1DPC 2R) | 1866/933 (1DPC 2R) | x8, x16 | X | X | 1 | X | X | 1 | |||||||||
Support level key:
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Protocol | Category | Subcategory | Supported? | S | C | T | H |
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DDR4 | Interface Width | <=72 with DIMM | X | X | X | X | X |
<= 72 Component | X | X | X | X | X | ||
Controller | Hard Controller | X | X | X | X | X | |
PHY | Hard PHY | X | X | X | X | X | |
PHY Only 4 | X | X | X | X | X | ||
3DS | 3DS | X (1D2R/1D2R only) | X | X | X | X | |
Design example | X | X | X | X | X | ||
Rate (core) | Quarter Rate | X | X | X | X | X | |
DBI | Read DBI | X | X | X | X | X | |
Write DBI | X | X | X | X | X | ||
Mirroring | Address mirroring for odd ranks for multi rank DIMM | X | X | X | X | X | |
DM | DM Pins | X | X | X | X | X | |
Preamble | Read Preamble Settings | X | X | X | X | X | |
Write Preamble Settings | X | X | X | X | X | ||
Refresh 1 | Temperature Controlled Refresh | ||||||
Fine Granularity Refresh | |||||||
Auto Self-refresh Method | |||||||
Self-refresh abort | |||||||
ODT 1 | Input Buffer During Power-down Mode | ||||||
Controller | ECC (soft implementation only) | X | X | X | X | X | |
Reordering | X | X | X | X | X | ||
Auto Power-down | X | X | X | X | |||
User Refresh | |||||||
Auto Precharge | X | X | X | X | |||
Command Priority | |||||||
Calibration | Address/Command Calibration | X | X | X | X | X | |
Multi-rank Calibration | X | X | X | X | X | ||
Debug | EMIF Toolkit | X | X | X | X | ||
QDR-IV | Memory Protocol | Component | X | X | X | X | X |
Memory Type | XP | X | X | X | X | X | |
Interface Width 2 | x18, x36 component | X | X | X | X | 3 | |
Controller | Soft controller | X | X | X | X | ||
PHY | Hard PHY | X | X | X | X | ||
Design Example | Design Example | ||||||
Inversion | Address bus | ||||||
Data bus | |||||||
Calibration | Calibration | X | X | X | X | ||
Rate (core) | Quarter rate | X | X | X | X | ||
Debug | EMIF Toolkit | supported by TG1, not TG2 | X | X | X | X | |
Support level key:
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Protocol | Category | Subcategory | Supported? | S | C | T | H |
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DDR4 | Interface Width | <=72 with DIMM | X | X | X | X | |
<= 72 Component | X | X | X | X | |||
Controller | Hard Controller | X | X | X | X | ||
PHY | Hard PHY | X | X | X | X | ||
Design Example | Design Example | ||||||
Rate (core) | Quarter Rate | X | X | X | X | ||
Half Rate | X | X | X | X | |||
DM | DM Pins | X | X | X | X | ||
Preamble | Read Preamble Settings | X | X | X | X | ||
Write Preamble Settings | X | X | X | X | |||
Refresh 1 | Temperature Controlled Refresh | ||||||
Fine Granularity Refresh | |||||||
Auto Self-refresh Method | |||||||
Self-refresh | |||||||
ODT 1 | Input Buffer During Power-down Mode | ||||||
Controller | ECC | ||||||
Reordering | X | X | X | X | X | ||
Auto Power-down | X | X | X | X | |||
User Refresh | |||||||
Auto pre-charge | |||||||
Command Priority | |||||||
Calibration | Address/Command Calibration | X | X | X | X | X | |
Multi-rank Calibration | X | X | X | X | X | ||
Debug | EMIF Toolkit | ||||||
Support level key:
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Category | Subcategory | Supported? | |
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Debug Support | On-chip Debug | On-chip Debug with Soft Nios® | X |
EMIF Toolkit | Calibration Margin | X | |
Rerun Calibration | X | ||
Vref Margining | X | ||
Driver Margining with TG1 | X | ||
Efficiency Monitor | X | ||
Efficiency Monitor with TG2 | X | ||
ODT Calibration | X | ||
Multi-interface Support | X | ||
Traffic Generator 2.0 (TG2) | Configurable address pattern | X | |
Configurable data pattern | X | ||
Configurable command pattern / test duration | X | ||
GUI to configure TG2 | X | ||
Default mode (old TG behavior) | X | ||
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