Visible to Intel only — GUID: flu1641547526047
Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Tone Mapping Operator Intel® FPGA IP
43. Test Pattern Generator Intel® FPGA IP
44. Unsharp Mask Intel® FPGA IP
45. Video and Vision Monitor Intel FPGA IP
46. Video Frame Buffer Intel® FPGA IP
47. Video Frame Reader Intel FPGA IP
48. Video Frame Writer Intel FPGA IP
49. Video Streaming FIFO Intel® FPGA IP
50. Video Timing Generator Intel® FPGA IP
51. Vignette Correction Intel® FPGA IP
52. Warp Intel® FPGA IP
53. White Balance Correction Intel® FPGA IP
54. White Balance Statistics Intel® FPGA IP
55. Design Security
56. Document Revision History for Video and Vision Processing Suite User Guide
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
31.4.3. Setting the VCXO hold over
31.4.4. Restarting the Genlock Controller IP
31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
31.4.7. Disturbing a Reference Clock (a cable pull)
Visible to Intel only — GUID: flu1641547526047
Ixiasoft
43.2. Test Pattern Generator IP Parameters
The IP offers run time and compile time parameters.
Parameter | Value | Description |
---|---|---|
Interface Configuration | ||
Lite mode | On or off | Turn on to use the Lite variant of the Intel FPGA Streaming Video protocol. |
Bits per color sample | 8 to 16 | Select the number of bits per color sample |
Number of pixels in parallel | 1 to 8 | Select the number of pixels in parallel at the output interface. |
Output format | 4:4:4, 4:2:2, 4:2:0. Variable or Monochrome | Select the chroma sampling format for the output interface. |
General | ||
Memory-mapped control interface | On or off | Turn on for the Avalon memory-mapped control agent interface and allow runtime configuration via the register map. You must have the Avalon memory-mapped control agent interface when you turn on Lite mode. |
Separate clock for control interface | On or off | Turn on for a separate clock for the control agent interface. |
Debug features | On or off | Turn on for read back of writeable registers via the control agent interface. |
Pipeline ready signals | On or off | Turn on to add extra pipeline registers to the AXI4-S tready signals. |
Shared configuration | ||
Fixed interlacing | 0 to 15 | Only if Memory-mapped control interface is not on. Select if output stream is progressive, interlaced with F0 sent first after reset, or interlaced with F1 sent first after reset. If Lite mode is off, the selected value populates the interlaced identifier field in the output image info packets.
|
Fixed frame width | 1 to 16384 | Only if Memory-mapped control interface is off. Select the width of the frames and fields produced at the output. If the selected output subsampling is 4:2:2 or 4:2:0, the frame width must be a multiple of 2. |
Fixed frame height | 1 to 16384 | Only if Memory-mapped control interface is off. Select the height of the frames and fields produced at the output. If the selected output subsampling is 4:2:0, the field height must be a multiple of 2. |
Pattern configuration | ||
Fixed bars mode | Color, Greyscale, Black and white, Mixed | Only if Memory-mapped control interface is off and you select the bars test pattern. Sets which variant of the bars pattern to use. |
Fixed constant color R/Cr | 0 – (2^ Bits per color sample)-1 | Only if Memory-mapped control interface is off and you select the constant color test pattern. Sets the value the IP uses for the R color plane if the output is RGB, or the Cr color plane if the output is YCbCr. |
Fixed constant color G/Y | 0 – (2^ Bits per color sample)-1 | Only if Memory-mapped control interface is off and you select the constant color test pattern. Sets the value the IP uses for the G color plane if the output is RGB, or the Y color plane if the output is YCbCr. |
Fixed constant color B/Cb | 0 – (2^ Bits per color sample)-1 | Only if Memory-mapped control interface is off and you select the constant color test pattern. Sets the value the IP uses for the B color plane if the output is RGB, or the Cb color plane if the output is YCbCr. |
Fixed zone plate coarse scaling factor | 1 to 31 | Only if Memory-mapped control interface is off. Increase this value to increase the size of the zone plate. The value is arbitrary, but Intel recommends a starting value of 14 for HD and 20 for 4k resolutions. |
Fixed zone plate fine tune scaling factor | 1 to 65535 |
Only if Memory-mapped control interface is off. A 16-bit fixed-point value, with 8 bits fractional part. For example, 256 represents a value of 1.0. Increase this value to decrease the size of the zone plate. |
Fixed clock background color (B/Cb component) | 0– (2^ Bits per color sample)-1 | Only if Memory-mapped control interface is off. Select the value the IP uses for the B background color plane if the output is RGB, or the Cb color plane if the output is YCbCr. |
Fixed clock background color (G/Y component) | 0– (2^ Bits per color sample)-1 | Only if Memory-mapped control interface is off. Sets the value the IP uses for the G background color plane if the output is RGB, or the Y color plane if the output is YCbCr. |
Fixed clock background color (R/Cr component) | 0– (2^ Bits per color sample)-1 | Only if Memory-mapped control interface is off. Select the value the IP uses for the R background color plane if the output is RGB, or the Cr color plane if the output is YCbCr. |
Fixed clock font color (B/Cb component) | 0– (2^ Bits per color sample)-1 | Only if Memory-mapped control interface is off. Select the value the IP uses for the B font color plane if the output is RGB, or the Cb color plane if the output is YCbCr. |
Fixed clock font color (G/Y component) | 0– (2^ Bits per color sample)-1 | Only if Memory-mapped control interface is off. Select the value the IP uses for the G font color plane if the output is RGB, or the Y color plane if the output is YCbCr. |
Fixed clock font color (R/Cr component) | 0– (2^ Bits per color sample)-1 | Only if Memory-mapped control interface is off. Select the value the IP uses for the R font color plane if the output is RGB, or the Cr color plane if the output is YcbCr. |
Fixed clock location x-coordinate | 0 to 16383 | Only if Memory-mapped control interface is off. Select the x-location of the top-left pixel of the digital clock. |
Fixed clock location y-coordinate | 0 to 16383 | Only if Memory-mapped control interface is off. Select the y-location of the top-left pixel of the digital clock. |
Fixed clock scale factor | 1 to 65535 | Only if Memory-mapped control interface is off and you select the digital clock test pattern. Selectt the multiplying coefficient to the original digital clock dimensions. |
Fixed clock FPS | 1 to 60 | Only if Memory-mapped control interface is off. Select the number of frames until one second is reached. This parameter does not affect the output video refresh rate). |
Number of test patterns | 1 to 8 | Set the number of test pattern configurations to turn on. |
Core 0 test pattern Core 1 test pattern Core 2 test pattern Core 3 test pattern Core 4 test pattern Core 5 test pattern Core 6 test pattern Core 7 test pattern |
Bars, Constant color, SDI pathological, Zone plate, Digital clock | Selects the test pattern for each configuration. |
Core 0 color space Core 1 color space Core 2 color space Core 3 color space Core 4 color space Core 5 color space Core 6 color space Core 7 color space |
RGB, YCbCr 444, YCbCr 422, YCbCr 420, MONO | Sets the output color space and chroma sampling for each test pattern configuration. |