Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public

Visible to Intel only — GUID: iqb1661431625132

Ixiasoft

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

41.3.1. Switch IP Latency

The Switch IP latency depends on clean or crash switches

Clean Switch Latency

When you turn off Crash switching, the IP switch occurs cleanly, with the last packet on each output completed legally, as denoted by tlast.

The switch IP latency for clean switches depends on the complexity of the switch made, the configuration of the switch, the timing of the switch command, the timing on the inputs, and any backpressure experienced on the outputs.

The minimum switch latency (Lclean_switch) is the number of clock cycles from the submitting of a new switch configuration via a write to the COMMIT register, to the start of the first image information packet (full variants) or first line (lite variants) produced at the configured outputs.

Lclean_ switch = Tremaining + 8 + (C ? 6 : 3)*I + 8*O

where

  • Tremaining = the number of cycles from the write to COMMIT to the end-of-field packet of the current input field (for full variants) or to the TLAST of the current line (lite variants) or to the next TUSER[0] (lite variants with All inputs are uninterrupted on).
  • I = The number of inputs whose state is changing (either consume, enable, disable or destination)
  • O = The number of outputs whose state is changing (either enable, disable, or source)
  • C is 1 with Autoconsume inputs on.

This equation holds in the absence of backpressure and in a fully synchronized system with all switch inputs receiving fields of the same size at the same time, and common host and main clocks.

Latency in a real system is dominated by the timing of the input fields and Lswitch usually only represents a very small percentage of overall switching time.

The fastest switching configurations are lite variants with All inputs are uninterrupted off, as changes occur at line endings, not field endings.

Crash Switch Latency

When you turn on Crash switching, the IP switches occur faster than for clean switching but broken packets may occur at the switch outputs. Crash switch latency is given by Lcrash_switch and switch latency is unaffected by backpressure.

Lcrash_switch <= (Total number of outputs configured)*4 + 4