Video and Vision Processing Suite IP User Guide

ID 683329
Date 3/30/2025
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter IP 8. 1D LUT IP 9. 3D LUT IP 10. Adaptive Noise Reduction IP 11. Advanced Test Pattern Generator IP 12. AXI-Stream Broadcaster IP 13. Bits per Color Sample Adapter IP 14. Black Level Correction IP 15. Black Level Statistics IP 16. Chroma Key IP 17. Chroma Resampler IP 18. Clipper IP 19. Clocked Video Input IP 20. Clocked Video to Full-Raster Converter IP 21. Clocked Video Output IP 22. Color Plane Manager IP 23. Color Space Converter IP 24. Defective Pixel Correction IP 25. Deinterlacer IP 26. Demosaic IP 27. FIR Filter IP 28. Frame Cleaner IP 29. Full-Raster to Clocked Video Converter IP 30. Full-Raster to Streaming Converter IP 31. Genlock Controller IP 32. Generic Crosspoint IP 33. Genlock Signal Router IP 34. Guard Bands IP 35. Histogram Statistics IP 36. Interlacer IP 37. Mixer IP 38. Pixels in Parallel Converter IP 39. Scaler IP 40. Stream Cleaner IP 41. Switch IP 42. Text Box IP 43. Tone Mapping Operator IP 44. Test Pattern Generator IP 45. Unsharp Mask IP 46. Video and Vision Monitor Intel FPGA IP 47. Video Frame Buffer IP 48. Video Frame Reader Intel FPGA IP 49. Video Frame Writer Intel FPGA IP 50. Video Streaming FIFO IP 51. Video Timing Generator IP 52. Vignette Correction IP 53. Warp IP 54. White Balance Correction IP 55. White Balance Statistics IP 56. Design Security 57. Document Revision History for Video and Vision Processing Suite User Guide

31.3.1. Genlock Controller IP Interfaces

Table 551.   Genlock Controller IP Interfaces
Name Direction Width Description
Clocks and Resets
vcxo_clock Input 1 Input VCXO clock
vcxo_reset Input 1 Input VCXO reset
ref0_clock Input 1 Input reference # 0 clock
ref0_reset Input 1 Input reference # 0 reset
ref1_clock Input 1 Input reference # 1 clock
ref1_reset Input 1 Input reference # 1 reset
ref2_clock Input 1 Input reference # 2 clock
ref2_reset Input 1 Input reference # 2 reset
ref3_clock Input 1 Input reference # 3 clock
ref3_reset Input 1 Input reference # 3 reset
cpu_clock Input 1 Control interface clock
cpu_reset Input 1 Control interface reset
Control Interfaces
av_mm_control_agent_address Input 7 Avalon memory-mapped agent address
av_mm_control_agent_write Input 1 Avalon memory-mapped agent write
av_mm_control_agent_writedata Input 32 Avalon memory-mapped agent write data
av_mm_control_agent_byteenable Input 4 Avalon memory-mapped agent byte enable
av_mm_control_agent_read Input 1 Avalon memory-mapped agent read request
av_mm_control_agent_readdata Output 32 Avalon memory-mapped agent read data
av_mm_control_agent_readdatavalid Output 1 Avalon memory-mapped agent read valid
av_mm_control_agent_waitrequest Output 1 Avalon memory-mapped agent wait request
External Output Conduits
vcxo pwm Output 1 A three-state PWM output to control an external VCXO
locked Output 1 A level signal indicating if the IP achieves the genlock between the reference clock and VCXO.
Genlock Profiler Input Conduits
vid_rx_ref_tim Input 1 Receive toggle SOF signal
vid_tx_ref_tim Input 1 Transmit toggle SOF signal
Genlock Profiler Output Conduits
GPO bus Output 8 Genlock error mapping general purpose output (GPO) bus