Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/03/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide

25.2. Guard Bands IP Parameters

Parameter Values Description
Video Data Format
Bits per color sample 8 to 16 Select the number of bits per color sample.
Number of color planes 1 to 4 Select the number of color planes per pixel.
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel.
4:2:2 data On or off Turn on to indicate that the input data is 4:2:2 sampled.
Signed input data On or off Turn on to indicate that the input data is signed 2’s complement numbers.
Signed output data On or off Turn on to indicate that the output data is signed 2’s complement numbers.
Control
Lite mode On or off Turn on to use the lite variant of the Intel FPGA streaming video protocol.
Memory-mapped control interface On or off Turn on to specify guard bands values at run-time using the Avalon memory-mapped interface.
Separate clock for control interface On or off Turn on to enable a separate clock for the control interface.
Debug features On or off Turn on for debugging features (not applicable when you turn on Lite mode).
Guard Bands
Lower/Upper guard band for color <0–3> 0 to (Bits per color sample)-1

These parameters define the guard bands for each color plane (up to 4 colors per pixel). Color 0 is in the LSBs of the AXI-streaming video data bus.

If you turn on Memory-mapped control interface, the IP does not use these values and you must write their value using Avalon memory-mapped interface.