Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

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ID 683323
Date 9/24/2018
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Document Table of Contents
Document Table of Contents x
1. Recommended Design Practices 2. Recommended HDL Coding Styles 3. Managing Metastability with the Intel® Quartus® Prime Software A. Intel® Quartus® Prime Standard Edition User Guides
1. Recommended Design Practices x
1.1. Following Synchronous FPGA Design Practices 1.2. HDL Design Guidelines 1.3. Checking Design Violations 1.4. Use Clock and Register-Control Architectural Features 1.5. Implementing Embedded RAM 1.6. Recommended Design Practices Revision History
1.1. Following Synchronous FPGA Design Practices x
1.1.1. Implementing Synchronous Designs 1.1.2. Asynchronous Design Hazards
1.2. HDL Design Guidelines x
1.2.1. Optimizing Combinational Logic 1.2.2. Optimizing Clocking Schemes 1.2.3. Optimizing Physical Implementation and Timing Closure 1.2.4. Optimizing Power Consumption 1.2.5. Managing Design Metastability
1.2.1. Optimizing Combinational Logic x
1.2.1.1. Avoid Combinational Loops 1.2.1.2. Avoid Unintended Latch Inference 1.2.1.3. Avoid Delay Chains in Clock Paths 1.2.1.4. Use Synchronous Pulse Generators
1.2.2. Optimizing Clocking Schemes x
1.2.2.1. Register Combinational Logic Outputs 1.2.2.2. Avoid Asynchronous Clock Division 1.2.2.3. Avoid Ripple Counters 1.2.2.4. Use Multiplexed Clocks 1.2.2.5. Use Gated Clocks 1.2.2.6. Use Synchronous Clock Enables
1.2.2.5. Use Gated Clocks x
1.2.2.5.1. Recommended Clock-Gating Methods
1.2.3. Optimizing Physical Implementation and Timing Closure x
1.2.3.1. Planning Physical Implementation 1.2.3.2. Planning FPGA Resources 1.2.3.3. Optimizing for Timing Closure 1.2.3.4. Optimizing Critical Timing Paths
1.3. Checking Design Violations x
1.3.1. Validating Against Design Rules 1.3.2. Creating Custom Design Rules
1.3.2. Creating Custom Design Rules x
1.3.2.1. Custom Design Rule Examples
1.4. Use Clock and Register-Control Architectural Features x
1.4.1. Use Global Reset Resources 1.4.2. Use Global Clock Network Resources 1.4.3. Use Clock Region Assignments to Optimize Clock Constraints 1.4.4. Avoid Asynchronous Register Control Signals
1.4.1. Use Global Reset Resources x
1.4.1.1. Use Synchronous Resets 1.4.1.2. Using Asynchronous Resets 1.4.1.3. Use Synchronized Asynchronous Reset
1.4.3. Use Clock Region Assignments to Optimize Clock Constraints x
1.4.3.1. Clock Region Assignments in Intel® Arria® 10 and Older Device Families
2. Recommended HDL Coding Styles x
2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
2.1. Using Provided HDL Templates x
2.1.1. Inserting HDL Code from a Provided Template
2.3. Inferring Multipliers and DSP Functions x
2.3.1. Inferring Multipliers 2.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions Verilog HDL Multiply-Accumulator Verilog HDL Signed Multiply-Adder VHDL Signed Multiply-Accumulator VHDL Unsigned Multiply-Adder
2.4. Inferring Memory Functions from HDL Code x
2.4.1. Inferring RAM functions from HDL Code 2.4.2. Inferring ROM Functions from HDL Code 2.4.3. Inferring Shift Registers in HDL Code
2.4.1. Inferring RAM functions from HDL Code x
2.4.1.1. Use Synchronous Memory Blocks 2.4.1.2. Avoid Unsupported Reset and Control Conditions 2.4.1.3. Check Read-During-Write Behavior 2.4.1.4. Controlling RAM Inference and Implementation 2.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 2.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 2.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM 2.4.1.8. True Dual-Port Synchronous RAM 2.4.1.9. Mixed-Width Dual-Port RAM 2.4.1.10. RAM with Byte-Enable Signals 2.4.1.11. Specifying Initial Memory Contents at Power-Up
2.4.3. Inferring Shift Registers in HDL Code x
2.4.3.1. Simple Shift Register 2.4.3.2. Shift Register with Evenly Spaced Taps
2.5. Register and Latch Coding Guidelines x
2.5.1. Register Power-Up Values 2.5.2. Secondary Register Control Signals Such as Clear and Clock Enable 2.5.3. Latches
2.5.1. Register Power-Up Values x
2.5.1.1. Specifying a Power-Up Value
2.5.3. Latches x
2.5.3.1. Avoid Unintentional Latch Generation 2.5.3.2. Inferring Latches Correctly
2.6. General Coding Guidelines x
2.6.1. Tri-State Signals 2.6.2. Clock Multiplexing 2.6.3. Adder Trees 2.6.4. State Machine HDL Guidelines 2.6.5. Multiplexer HDL Guidelines 2.6.6. Cyclic Redundancy Check Functions 2.6.7. Comparator HDL Guidelines 2.6.8. Counter HDL Guidelines
2.6.3. Adder Trees x
2.6.3.1. Architectures with 4-Input LUTs in Logic Elements 2.6.3.2. Architectures with 6-Input LUTs in Adaptive Logic Modules
2.6.4. State Machine HDL Guidelines x
2.6.4.1. Verilog HDL State Machines 2.6.4.2. VHDL State Machines
2.6.4.1. Verilog HDL State Machines x
2.6.4.1.1. Verilog-2001 State Machine Coding Example 2.6.4.1.2. SystemVerilog State Machine Coding Example
2.6.4.2. VHDL State Machines x
2.6.4.2.1. VHDL State Machine Coding Example
2.6.5. Multiplexer HDL Guidelines x
2.6.5.1. Intel® Quartus® Prime Software Option for Multiplexer Restructuring 2.6.5.2. Multiplexer Types 2.6.5.3. Implicit Defaults in IF Statements 2.6.5.4. default or OTHERS CASE Assignment
2.6.5.2. Multiplexer Types x
2.6.5.2.1. Binary Multiplexers 2.6.5.2.2. Selector Multiplexers 2.6.5.2.3. Priority Multiplexers
2.6.6. Cyclic Redundancy Check Functions x
2.6.6.1. If Performance is Important, Optimize for Speed 2.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages 2.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 2.6.6.4. Take Advantage of Latency if Available 2.6.6.5. Save Power by Disabling CRC Blocks When Not in Use 2.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
3. Managing Metastability with the Intel® Quartus® Prime Software x
3.1. Metastability Analysis in the Intel® Quartus® Prime Software 3.2. Metastability and MTBF Reporting 3.3. MTBF Optimization 3.4. Reducing Metastability Effects 3.5. Scripting Support 3.6. Managing Metastability 3.7. Managing Metastability with the Intel® Quartus® Prime Software Revision History
3.1. Metastability Analysis in the Intel® Quartus® Prime Software x
3.1.1. Synchronization Register Chains 3.1.2. Identify Synchronizers for Metastability Analysis 3.1.3. How Timing Constraints Affect Synchronizer Identification and Metastability Analysis
3.2. Metastability and MTBF Reporting x
3.2.1. Metastability Reports 3.2.2. Synchronizer Data Toggle Rate in MTBF Calculation
3.2.1. Metastability Reports x
3.2.1.1. MTBF Summary Report 3.2.1.2. Synchronizer Summary Report 3.2.1.3. Synchronizer Chain Statistics Report in the Timing Analyzer
3.2.1.1. MTBF Summary Report x
3.2.1.1.1. Typical and Worst-Case MTBF of Design 3.2.1.1.2. Synchronizer Chains 3.2.1.1.3. Increasing Available Settling Time
3.3. MTBF Optimization x
3.3.1. Synchronization Register Chain Length
3.4. Reducing Metastability Effects x
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
3.5. Scripting Support x
3.5.1. Identifying Synchronizers for Metastability Analysis 3.5.2. Synchronizer Data Toggle Rate in MTBF Calculation 3.5.3. report_metastability and Tcl Command 3.5.4. MTBF Optimization 3.5.5. Synchronization Register Chain Length
1. Recommended Design Practices
2. Recommended HDL Coding Styles
3. Managing Metastability with the Intel® Quartus® Prime Software
A. Intel® Quartus® Prime Standard Edition User Guides

2.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions

Synthesis tools detect multiply-accumulator or multiply-adder functions, and either implement them as Intel FPGA IP cores or map them directly to device atoms. During placement and routing, the Intel® Quartus® Prime software places multiply-accumulator and multiply-adder functions in DSP blocks.
Note: Synthesis tools infer multiply-accumulator and multiply-adder functions only if the Intel device family has dedicated DSP blocks that support these functions.

A simple multiply-accumulator consists of a multiplier feeding an addition operator. The addition operator feeds a set of registers that then feeds the second input to the addition operator. A simple multiply-adder consists of two to four multipliers feeding one or two levels of addition, subtraction, or addition/subtraction operators. Addition is always the second-level operator, if it is used. In addition to the multiply-accumulator and multiply-adder, the Intel® Quartus® Prime Fitter also places input and output registers into the DSP blocks to pack registers and improve performance and area utilization.

Some device families offer additional advanced multiply-adder and accumulator functions, such as complex multiplication, input shift register, or larger multiplications.

The Verilog HDL and VHDL code samples infer multiply-accumulator and multiply-adder functions with input, output, and pipeline registers, as well as an optional asynchronous clear signal. Using the three sets of registers provides the best performance through the function, with a latency of three. To reduce latency, remove the registers in your design.
Note: To obtain high performance in DSP designs, use register pipelining and avoid unregistered DSP functions.

Verilog HDL Multiply-Accumulator 

module sum_of_four_multiply_accumulate
   #(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=44)
   (
      input clk, ena,
      input [INPUT_WIDTH-1:0] dataa, datab, datac, datad,
      input [INPUT_WIDTH-1:0] datae, dataf, datag, datah,
      output reg [OUTPUT_WIDTH-1:0] dataout
   );
   // Each product can be up to 2*INPUT_WIDTH bits wide.
   // The sum of four of these products can be up to 2 bits wider.
   wire [2*INPUT_WIDTH+1:0] mult_sum;

   // Store the results of the operations on the current inputs
   assign mult_sum = (dataa * datab + datac * datad) +
                     (datae * dataf + datag * datah);

   // Store the value of the accumulation
   always @ (posedge clk)
   begin
      if (ena == 1)
         begin
            dataout <= dataout + mult_sum;
         end
   end
endmodule

Verilog HDL Signed Multiply-Adder

module sig_altmult_add (dataa, datab, datac, datad, clock, aclr, result);
   input signed [15:0] dataa, datab, datac, datad;
   input clock, aclr;
   output reg signed [32:0] result;

   reg signed [15:0] dataa_reg, datab_reg, datac_reg, datad_reg;
   reg signed [31:0] mult0_result, mult1_result;

   always @ (posedge clock or posedge aclr) begin
       if (aclr) begin
           dataa_reg <= 16'b0;
           datab_reg <= 16'b0;
           datac_reg <= 16'b0;
           datad_reg <= 16'b0;
           mult0_result <= 32'b0; 
           mult1_result <= 32'b0; 
           result <= 33'b0;
        end
        else begin
           dataa_reg <= dataa;
           datab_reg <= datab;
           datac_reg <= datac;
           datad_reg <= datad;
           mult0_result <= dataa_reg * datab_reg;        
           mult1_result <= datac_reg * datad_reg; 
           result <= mult0_result + mult1_result;
       end
   end    
endmodule

VHDL Signed Multiply-Accumulator

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY sig_altmult_accum IS
   PORT (
      a: IN SIGNED(7 DOWNTO 0);
      b: IN SIGNED (7 DOWNTO 0);
      clk: IN STD_LOGIC;
      aclr: IN STD_LOGIC;
      accum_out: OUT SIGNED (15 DOWNTO 0)
   ) ;
END sig_altmult_accum;

ARCHITECTURE rtl OF sig_altmult_accum IS
   SIGNAL a_reg, b_reg: SIGNED (7 DOWNTO 0);
   SIGNAL pdt_reg: SIGNED (15 DOWNTO 0);
   SIGNAL adder_out: SIGNED (15 DOWNTO 0);
BEGIN
   PROCESS (clk, aclr)
   BEGIN
      IF (aclr = '1') then
          a_reg <= (others => '0');
          b_reg <= (others => '0');
          pdt_reg <= (others => '0');
          adder_out <= (others => '0');
      ELSIF (rising_edge(clk)) THEN
          a_reg <= (a);
          b_reg <= (b);
          pdt_reg <= a_reg * b_reg;
          adder_out <= adder_out + pdt_reg;
      END IF;
   END process;
   accum_out <= adder_out;
END rtl;

VHDL Unsigned Multiply-Adder

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY unsignedmult_add IS
   PORT (
      a: IN UNSIGNED (7 DOWNTO 0);
      b: IN UNSIGNED (7 DOWNTO 0);
      c: IN UNSIGNED (7 DOWNTO 0);
      d: IN UNSIGNED (7 DOWNTO 0);
      clk: IN STD_LOGIC;
      aclr: IN STD_LOGIC;
      result: OUT UNSIGNED (15 DOWNTO 0)
   );
END unsignedmult_add;

ARCHITECTURE rtl OF unsignedmult_add IS
   SIGNAL a_reg, b_reg, c_reg, d_reg: UNSIGNED (7 DOWNTO 0);
   SIGNAL pdt_reg, pdt2_reg: UNSIGNED (15 DOWNTO 0);
   SIGNAL result_reg: UNSIGNED (15 DOWNTO 0);
BEGIN
   PROCESS (clk, aclr)
   BEGIN
      IF (aclr = '1') THEN
         a_reg <= (OTHERS => '0');
         b_reg <= (OTHERS => '0');
         c_reg <= (OTHERS => '0');
         d_reg <= (OTHERS => '0');
         pdt_reg <= (OTHERS => '0');
         pdt2_reg <= (OTHERS => '0');
         result_reg <= (OTHERS => '0');

      ELSIF (rising_edge(clk)) THEN
         a_reg <= a; 
         b_reg <= b; 
         c_reg <= c;
         d_reg <= d;
         pdt_reg <= a_reg * b_reg;
         pdt2_reg <= c_reg * d_reg;
         result_reg <= pdt_reg + pdt2_reg;
      END IF;
      END PROCESS;
   result <= result_reg;
END rtl;
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