Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 7/08/2024
Public
Document Table of Contents

CLOCK_REGION

Specifies the placement of the clock region of a global signal for floorplanning reasons. For example, a Clock Region assignment can be used to ensure that a certain area of the device has access to a global signal, throughout all future design iterations. A Clock Region assignment can also be used in cases of congestion involving global signal resources. By specifying a smaller clock region size, the assignment prevents a signal using spine clock and other clock routing resources in the excluded sectors that may be encountering clock-related congestion.\n\nFor devices up to and including Arria 10, this assignment takes as its value the names of those Global, Regional, Periphery or Spine Clock regions. These region names are visible in Chip Planner by enabling the appropriate Clock Region layer in the Layers Settings dialog box. Examples of valid values include \"Regional Clock Region 1\" or \"Periphery Clock Region 1\". When constraining a global signal to a smaller than normal region, for example, to avoid clock congestion, you may specify a clock region of a different type than the global resources being used. For example, a signal with a Global Signal assignment of \"Global Clock\", but a Clock Region assignment of \"Regional Clock Region 0\", constrains the clock to use global network routing resources, but only to the region covered by Regional Clock Region 0. To provide a finer level of control, you can also list multiple smaller clock regions, separated by commas. For example: \"Periphery Clock Region 0, Periphery Clock Region 1\" constrains a signal to only the area reachable by those two periphery clock networks.\n\nFor Stratix 10 devices, clock regions can be constrained to a rectangle whose dimensions are defined by the sector grid, as seen in the Clock Sector Region layer of the Chip Planner. This assignment specifies the bottom left and top right coordinates of the rectangle in the format \"SX# SY# SX# SY#\". For example, \"SX0 SY0 SX1 SY1\" constrains the clock to a 2x2 region, from the bottom left of sector (0,0) to the top right of sector (1,1). For a constraint spanning only one sector, it is sufficient to specify the location of that sector, for example \"SX1 SY1\". The bounding rectangle can also be specified by the bottom left and top right corners in chip coordinates, for example, \"X37 Y181 X273 Y324\". However, such a constraint should be sector aligned (using sector coordinates guarantees this) or the Fitter automatically snaps to the smallest sector aligned rectangle that still encompasses the original assignment. The \"SX# SY# SX# SY#\"|\"X# Y# X# Y#\" strings are case-insensitive.

Type

String

Device Support

  • Intel Agilex® 5
  • Intel Agilex® 7
  • Arria® 10
  • Cyclone® 10 GX
  • Stratix® 10

Notes

This assignment supports wildcards.

This assignment supports Fitter wildcards.

Syntax

set_instance_assignment -name CLOCK_REGION -to <to> -entity <entity name> <value>
set_instance_assignment -name CLOCK_REGION -from <from> -to <to> -entity <entity name> <value>